74 lines
2.3 KiB
Systemverilog
74 lines
2.3 KiB
Systemverilog
`ifndef VX_CACHE_CONFIG
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`define VX_CACHE_CONFIG
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`include "VX_define.vh"
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// data tid rd wb warp_num read write
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`define MRVQ_METADATA_SIZE (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS) + 3 + 3)
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// rd wb warp_num read write + reqs
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`define REQ_INST_META_SIZE (5 + 2 + (`NW_BITS) + 3 + 3 + `LOG2UP(NUM_REQUESTS))
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`define WORD_SIZE (8 * WORD_SIZE_BYTES)
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`define WORD_SIZE_RNG (`WORD_SIZE)-1:0
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// 128
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`define BANK_SIZE_BYTES (CACHE_SIZE_BYTES / NUM_BANKS)
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// 8
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`define BANK_LINE_COUNT (`BANK_SIZE_BYTES / BANK_LINE_SIZE_BYTES)
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// 4
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`define BANK_LINE_WORDS (BANK_LINE_SIZE_BYTES / WORD_SIZE_BYTES)
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// Offset is fixed
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`define OFFSET_ADDR_BITS 2
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`define OFFSET_SIZE_END 1
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`define OFFSET_ADDR_START 0
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`define OFFSET_ADDR_END 1
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`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START
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`define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0
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// 2
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`define WORD_SELECT_BITS (`LOG2UP(`BANK_LINE_WORDS))
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// 2
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`define WORD_SELECT_SIZE_END (`WORD_SELECT_BITS)
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// 2
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`define WORD_SELECT_ADDR_START (1+`OFFSET_ADDR_END)
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// 3
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`define WORD_SELECT_ADDR_END (`WORD_SELECT_SIZE_END+`OFFSET_ADDR_END)
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// 3:2
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`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START
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// 3
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`define BANK_SELECT_BITS (`LOG2UP(NUM_BANKS))
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// 3
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`define BANK_SELECT_SIZE_END (`BANK_SELECT_BITS)
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// 4
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`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END)
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// 6
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`define BANK_SELECT_ADDR_END (`BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START-1)
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// 6:4
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`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START
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// 3
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`define LINE_SELECT_BITS (`LOG2UP(`BANK_LINE_COUNT))
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// 7
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`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END)
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// 9
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`define LINE_SELECT_ADDR_END (`LINE_SELECT_BITS+`LINE_SELECT_ADDR_START-1)
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// 9:7
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`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START
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// 10
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`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
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// 31:10
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`define TAG_SELECT_ADDR_RNG 31:`TAG_SELECT_ADDR_START
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// 22
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`define TAG_SELECT_BITS (32-`TAG_SELECT_ADDR_START)
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`define TAG_LINE_SELECT_BITS (`TAG_SELECT_BITS+`LINE_SELECT_BITS)
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`define BASE_ADDR_MASK (~((1<<(`WORD_SELECT_ADDR_END+1))-1))
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`endif
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