c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
119 lines
3.2 KiB
Verilog
119 lines
3.2 KiB
Verilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`timescale 10ns / 1ns
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`define CYCLE_TIME 4
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module testbench;
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reg clk;
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reg resetn;
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reg [43:0] cycles;
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reg vx_running;
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reg vx_reset_wait;
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reg vx_busy_wait;
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wire vx_busy;
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reg dcr_wr_valid;
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reg [11:0] dcr_wr_addr;
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reg [31:0] dcr_wr_data;
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design_1_wrapper UUD(
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.clk_100MHz (clk),
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.resetn (resetn),
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.vx_reset (~resetn || ~vx_running),
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.dcr_wr_valid (dcr_wr_valid),
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.dcr_wr_addr (dcr_wr_addr),
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.dcr_wr_data (dcr_wr_data),
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.vx_busy (vx_busy)
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);
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always #(`CYCLE_TIME/2)
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clk = ~clk;
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initial begin
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clk = 1'b0;
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resetn = 1'b0;
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#4 resetn = 1'b1;
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end
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always @(posedge clk) begin
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if (~resetn) begin
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cycles <= 0;
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end else begin
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cycles <= cycles + 1;
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end
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end
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reg [7:0] vx_reset_ctr;
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always @(posedge clk) begin
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if (vx_reset_wait) begin
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vx_reset_ctr <= vx_reset_ctr + 1;
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end else begin
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vx_reset_ctr <= 0;
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end
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end
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always @(posedge clk) begin
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if (~resetn) begin
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vx_running <= 0;
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vx_reset_wait <= 0;
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vx_busy_wait <= 0;
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dcr_wr_valid <= 0;
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dcr_wr_addr <= 0;
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dcr_wr_data <= 0;
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end else begin
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case (cycles)
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1: begin
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dcr_wr_valid <= 1;
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dcr_wr_addr <= `VX_DCR_BASE_STARTUP_ADDR0;
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dcr_wr_data <= `STARTUP_ADDR;
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end
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2: begin
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dcr_wr_valid <= 0;
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dcr_wr_addr <= 0;
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dcr_wr_data <= 0;
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end
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3: begin
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vx_reset_wait <= 1;
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end
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default:;
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endcase
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if (vx_running) begin
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if (vx_busy_wait) begin
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if (vx_busy) begin
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vx_busy_wait <= 0;
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end
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end else begin
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if (~vx_busy) begin
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vx_running <= 0;
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$display("done!");
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$finish;
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end
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end
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end else begin
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if (vx_reset_wait && vx_reset_ctr == (`RESET_DELAY-1)) begin
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$display("start!");
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vx_reset_wait <= 0;
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vx_running <= 1;
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vx_busy_wait <= 1;
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end
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end
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end
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end
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endmodule |