d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
48 lines
1.2 KiB
C++
48 lines
1.2 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <iostream>
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#include <unordered_map>
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#include <vector>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include "VVX_mem_streamer.h"
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#include "VVX_mem_streamer__Syms.h"
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#include "ram.h"
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#define SIM_TIME 5000
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int generate_rand (int min, int max);
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int generate_rand_mask (int mask);
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class MemSim {
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private:
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VVX_mem_streamer *msu_;
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VerilatedVcdC *trace_;
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void eval();
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void step();
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void reset();
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void attach_core();
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void attach_ram(RAM *ram);
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public:
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MemSim();
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virtual ~MemSim();
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void run(RAM *ram);
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};
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