d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
94 lines
2.9 KiB
Systemverilog
94 lines
2.9 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_pipe_register #(
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parameter DATAW = 1,
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parameter RESETW = 0,
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parameter DEPTH = 1
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) (
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input wire clk,
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input wire reset,
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input wire enable,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out
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);
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if (DEPTH == 0) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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`UNUSED_VAR (enable)
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assign data_out = data_in;
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end else if (DEPTH == 1) begin
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if (RESETW == 0) begin
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`UNUSED_VAR (reset)
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reg [DATAW-1:0] value;
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always @(posedge clk) begin
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if (enable) begin
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value <= data_in;
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end
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end
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assign data_out = value;
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end else if (RESETW == DATAW) begin
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reg [DATAW-1:0] value;
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always @(posedge clk) begin
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if (reset) begin
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value <= RESETW'(0);
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end else if (enable) begin
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value <= data_in;
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end
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end
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assign data_out = value;
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end else begin
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reg [DATAW-RESETW-1:0] value_d;
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reg [RESETW-1:0] value_r;
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always @(posedge clk) begin
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if (reset) begin
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value_r <= RESETW'(0);
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end else if (enable) begin
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value_r <= data_in[DATAW-1:DATAW-RESETW];
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end
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end
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always @(posedge clk) begin
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if (enable) begin
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value_d <= data_in[DATAW-RESETW-1:0];
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end
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end
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assign data_out = {value_r, value_d};
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end
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end else begin
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wire [DEPTH:0][DATAW-1:0] data_delayed;
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assign data_delayed[0] = data_in;
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for (genvar i = 1; i <= DEPTH; ++i) begin
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VX_pipe_register #(
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.DATAW (DATAW),
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.RESETW (RESETW)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (enable),
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.data_in (data_delayed[i-1]),
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.data_out (data_delayed[i])
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);
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end
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assign data_out = data_delayed[DEPTH];
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end
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endmodule
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`TRACING_ON
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