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d44144f72fa76c7a2923c4fc5b8ebaf148e3a3ba
vortex/hw/rtl/cache
History
Blaise Tine d44144f72f FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
..
VX_bank.v
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_cache_config.vh
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
VX_cache_core_req_bank_sel.v
critical path optimization - fpga fmax @4c = ~212 mhz
2020-12-26 03:28:32 -08:00
VX_cache_core_rsp_merge.v
critical path optimization - fpga fmax @4c = ~212 mhz
2020-12-26 03:28:32 -08:00
VX_cache.v
critical path optimization - fpga fmax @4c = ~212 mhz
2020-12-26 03:28:32 -08:00
VX_data_access.v
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
VX_data_store.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
VX_miss_resrv.v
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
VX_tag_access.v
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
VX_tag_store.v
adding new performance counters (banks utilization and DRAM bus utilization)
2020-12-22 12:33:45 -08:00
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