48 lines
2.2 KiB
Verilog
48 lines
2.2 KiB
Verilog
`include "VX_define.vh"
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module VX_dcache_arb (
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input wire req_select,
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// input request
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VX_cache_core_req_if in_core_req_if,
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// output 0 request
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VX_cache_core_req_if out0_core_req_if,
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// output 1 request
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VX_cache_core_req_if out1_core_req_if,
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// input 0 response
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VX_cache_core_rsp_if in0_core_rsp_if,
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// input 1 response
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VX_cache_core_rsp_if in1_core_rsp_if,
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// output response
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VX_cache_core_rsp_if out_core_rsp_if
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);
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assign out0_core_req_if.core_req_valid = in_core_req_if.core_req_valid & {`NUM_THREADS{~req_select}};
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assign out0_core_req_if.core_req_rw = in_core_req_if.core_req_rw;
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assign out0_core_req_if.core_req_byteen = in_core_req_if.core_req_byteen;
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assign out0_core_req_if.core_req_addr = in_core_req_if.core_req_addr;
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assign out0_core_req_if.core_req_data = in_core_req_if.core_req_data;
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assign out0_core_req_if.core_req_tag = in_core_req_if.core_req_tag;
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assign out1_core_req_if.core_req_valid = in_core_req_if.core_req_valid & {`NUM_THREADS{req_select}};
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assign out1_core_req_if.core_req_rw = in_core_req_if.core_req_rw;
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assign out1_core_req_if.core_req_byteen = in_core_req_if.core_req_byteen;
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assign out1_core_req_if.core_req_addr = in_core_req_if.core_req_addr;
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assign out1_core_req_if.core_req_data = in_core_req_if.core_req_data;
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assign out1_core_req_if.core_req_tag = in_core_req_if.core_req_tag;
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assign in_core_req_if.core_req_ready = req_select ? out1_core_req_if.core_req_ready : out0_core_req_if.core_req_ready;
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wire rsp_select0 = (| in0_core_rsp_if.core_rsp_valid);
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assign out_core_rsp_if.core_rsp_valid = rsp_select0 ? in0_core_rsp_if.core_rsp_valid : in1_core_rsp_if.core_rsp_valid;
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assign out_core_rsp_if.core_rsp_data = rsp_select0 ? in0_core_rsp_if.core_rsp_data : in1_core_rsp_if.core_rsp_data;
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assign out_core_rsp_if.core_rsp_tag = rsp_select0 ? in0_core_rsp_if.core_rsp_tag : in1_core_rsp_if.core_rsp_tag;
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assign in0_core_rsp_if.core_rsp_ready = out_core_rsp_if.core_rsp_ready && rsp_select0;
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assign in1_core_rsp_if.core_rsp_ready = out_core_rsp_if.core_rsp_ready && ~rsp_select0;
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endmodule |