201 lines
7.1 KiB
C++
201 lines
7.1 KiB
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Design implementation internals
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// See VVX_register_file.h for the primary calling header
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#include "VVX_register_file.h"
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#include "VVX_register_file__Syms.h"
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//--------------------
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// STATIC VARIABLES
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//--------------------
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VL_CTOR_IMP(VVX_register_file) {
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VVX_register_file__Syms* __restrict vlSymsp = __VlSymsp = new VVX_register_file__Syms(this, name());
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VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Reset internal values
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// Reset structure values
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_ctor_var_reset();
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}
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void VVX_register_file::__Vconfigure(VVX_register_file__Syms* vlSymsp, bool first) {
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if (0 && first) {} // Prevent unused
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this->__VlSymsp = vlSymsp;
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}
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VVX_register_file::~VVX_register_file() {
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delete __VlSymsp; __VlSymsp=NULL;
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}
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//--------------------
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void VVX_register_file::eval() {
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VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_register_file::eval\n"); );
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VVX_register_file__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
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VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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#ifdef VL_DEBUG
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// Debug assertions
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_eval_debug_assertions();
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#endif // VL_DEBUG
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// Initialize
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if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
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// Evaluate till stable
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int __VclockLoop = 0;
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QData __Vchange = 1;
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do {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
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_eval(vlSymsp);
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if (VL_UNLIKELY(++__VclockLoop > 100)) {
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// About to fail, so enable debug to see what's not settling.
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// Note you must run make with OPT=-DVL_DEBUG for debug prints.
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int __Vsaved_debug = Verilated::debug();
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Verilated::debug(1);
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__Vchange = _change_request(vlSymsp);
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Verilated::debug(__Vsaved_debug);
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VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
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} else {
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__Vchange = _change_request(vlSymsp);
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}
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} while (VL_UNLIKELY(__Vchange));
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}
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void VVX_register_file::_eval_initial_loop(VVX_register_file__Syms* __restrict vlSymsp) {
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vlSymsp->__Vm_didInit = true;
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_eval_initial(vlSymsp);
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// Evaluate till stable
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int __VclockLoop = 0;
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QData __Vchange = 1;
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do {
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_eval_settle(vlSymsp);
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_eval(vlSymsp);
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if (VL_UNLIKELY(++__VclockLoop > 100)) {
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// About to fail, so enable debug to see what's not settling.
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// Note you must run make with OPT=-DVL_DEBUG for debug prints.
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int __Vsaved_debug = Verilated::debug();
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Verilated::debug(1);
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__Vchange = _change_request(vlSymsp);
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Verilated::debug(__Vsaved_debug);
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VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
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} else {
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__Vchange = _change_request(vlSymsp);
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}
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} while (VL_UNLIKELY(__Vchange));
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}
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//--------------------
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// Internal Methods
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VL_INLINE_OPT void VVX_register_file::_sequent__TOP__1(VVX_register_file__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_sequent__TOP__1\n"); );
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VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Variables
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// Begin mtask footprint all:
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VL_SIG8(__Vdlyvdim0__VX_register_file__DOT__registers__v0,4,0);
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VL_SIG8(__Vdlyvset__VX_register_file__DOT__registers__v0,0,0);
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VL_SIG(__Vdlyvval__VX_register_file__DOT__registers__v0,31,0);
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// Body
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__Vdlyvset__VX_register_file__DOT__registers__v0 = 0U;
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// ALWAYS at VX_register_file.v:30
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if (((IData)(vlTOPp->in_write_register) & (0U != (IData)(vlTOPp->in_rd)))) {
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__Vdlyvval__VX_register_file__DOT__registers__v0
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= vlTOPp->in_data;
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__Vdlyvset__VX_register_file__DOT__registers__v0 = 1U;
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__Vdlyvdim0__VX_register_file__DOT__registers__v0
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= vlTOPp->in_rd;
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}
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// ALWAYSPOST at VX_register_file.v:32
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if (__Vdlyvset__VX_register_file__DOT__registers__v0) {
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vlTOPp->VX_register_file__DOT__registers[__Vdlyvdim0__VX_register_file__DOT__registers__v0]
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= __Vdlyvval__VX_register_file__DOT__registers__v0;
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}
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}
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VL_INLINE_OPT void VVX_register_file::_settle__TOP__2(VVX_register_file__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_settle__TOP__2\n"); );
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VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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vlTOPp->out_src1_data = vlTOPp->VX_register_file__DOT__registers
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[vlTOPp->in_src1];
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vlTOPp->out_src2_data = vlTOPp->VX_register_file__DOT__registers
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[vlTOPp->in_src2];
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}
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void VVX_register_file::_eval(VVX_register_file__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval\n"); );
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VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
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vlTOPp->_sequent__TOP__1(vlSymsp);
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}
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vlTOPp->_settle__TOP__2(vlSymsp);
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// Final
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vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
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}
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void VVX_register_file::_eval_initial(VVX_register_file__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_initial\n"); );
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VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
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}
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void VVX_register_file::final() {
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VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::final\n"); );
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// Variables
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VVX_register_file__Syms* __restrict vlSymsp = this->__VlSymsp;
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VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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}
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void VVX_register_file::_eval_settle(VVX_register_file__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_settle\n"); );
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VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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vlTOPp->_settle__TOP__2(vlSymsp);
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}
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VL_INLINE_OPT QData VVX_register_file::_change_request(VVX_register_file__Syms* __restrict vlSymsp) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_change_request\n"); );
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VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
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// Body
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// Change detection
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QData __req = false; // Logically a bool
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return __req;
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}
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#ifdef VL_DEBUG
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void VVX_register_file::_eval_debug_assertions() {
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VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_debug_assertions\n"); );
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// Body
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if (VL_UNLIKELY((clk & 0xfeU))) {
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Verilated::overWidthError("clk");}
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if (VL_UNLIKELY((in_write_register & 0xfeU))) {
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Verilated::overWidthError("in_write_register");}
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if (VL_UNLIKELY((in_rd & 0xe0U))) {
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Verilated::overWidthError("in_rd");}
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if (VL_UNLIKELY((in_src1 & 0xe0U))) {
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Verilated::overWidthError("in_src1");}
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if (VL_UNLIKELY((in_src2 & 0xe0U))) {
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Verilated::overWidthError("in_src2");}
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}
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#endif // VL_DEBUG
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void VVX_register_file::_ctor_var_reset() {
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VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_ctor_var_reset\n"); );
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// Body
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clk = VL_RAND_RESET_I(1);
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in_write_register = VL_RAND_RESET_I(1);
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in_rd = VL_RAND_RESET_I(5);
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in_data = VL_RAND_RESET_I(32);
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in_src1 = VL_RAND_RESET_I(5);
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in_src2 = VL_RAND_RESET_I(5);
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out_src1_data = VL_RAND_RESET_I(32);
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out_src2_data = VL_RAND_RESET_I(32);
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{ int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
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VX_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
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}}
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}
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