28 lines
607 B
Verilog
28 lines
607 B
Verilog
`include "VX_define.vh"
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module VX_priority_encoder #(
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parameter N
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) (
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input wire [N-1:0] valids,
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output wire [`LOG2UP(N)-1:0] index,
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output wire found
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);
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reg [`LOG2UP(N)-1:0] index_r;
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reg found_r;
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integer i;
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always @(*) begin
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index_r = 0;
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found_r = 0;
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for (i = `NUM_WARPS-1; i >= 0; i = i - 1) begin
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if (valids[i]) begin
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index_r = i[`NW_BITS-1:0];
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found_r = 1;
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end
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end
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end
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assign index = index_r;
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assign found = found_r;
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endmodule |