651 lines
18 KiB
Systemverilog
651 lines
18 KiB
Systemverilog
`include "platform_if.vh"
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import local_mem_cfg_pkg::*;
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`include "afu_json_info.vh"
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`include "VX_define.vh"
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module vortex_afu #(
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parameter NUM_LOCAL_MEM_BANKS = 2
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) (
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// global signals
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input clk,
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input SoftReset,
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// IF signals between CCI and AFU
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input t_if_ccip_Rx cp2af_sRxPort,
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output t_if_ccip_Tx af2cp_sTxPort,
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// Avalon signals for local memory access
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output t_local_mem_data avs_writedata,
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input t_local_mem_data avs_readdata,
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output t_local_mem_addr avs_address,
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input logic avs_waitrequest,
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output logic avs_write,
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output logic avs_read,
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output t_local_mem_byte_mask avs_byteenable,
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output t_local_mem_burst_cnt avs_burstcount,
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input avs_readdatavalid,
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output logic [$clog2(NUM_LOCAL_MEM_BANKS)-1:0] mem_bank_select
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);
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localparam DRAM_ADDR_WIDTH = $bits(t_local_mem_addr);
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localparam DRAM_LINE_WIDTH = $bits(t_local_mem_data);
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localparam DRAM_TAG_WIDTH = `L3DRAM_TAG_WIDTH;
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`STATIC_ASSERT(DRAM_ADDR_WIDTH == `L3DRAM_ADDR_WIDTH, "invalid vortex dram bus!")
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`STATIC_ASSERT(DRAM_LINE_WIDTH == `L3DRAM_LINE_WIDTH, "invalid vortex dram bus!")
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localparam AVS_RD_QUEUE_SIZE = 16;
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localparam CCI_RD_WINDOW_SIZE = 8;
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localparam CCI_RD_QUEUE_SIZE = 2 * CCI_RD_WINDOW_SIZE;
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localparam VX_SNOOP_DELAY = 1000;
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localparam VX_SNOOP_LEVELS = 2;
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localparam AFU_ID_L = 16'h0002; // AFU ID Lower
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localparam AFU_ID_H = 16'h0004; // AFU ID Higher
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localparam CMD_TYPE_READ = `AFU_IMAGE_CMD_TYPE_READ;
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localparam CMD_TYPE_WRITE = `AFU_IMAGE_CMD_TYPE_WRITE;
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localparam CMD_TYPE_RUN = `AFU_IMAGE_CMD_TYPE_RUN;
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localparam CMD_TYPE_CLFLUSH = `AFU_IMAGE_CMD_TYPE_CLFLUSH;
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localparam MMIO_CSR_CMD = `AFU_IMAGE_MMIO_CSR_CMD;
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localparam MMIO_CSR_STATUS = `AFU_IMAGE_MMIO_CSR_STATUS;
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localparam MMIO_CSR_IO_ADDR = `AFU_IMAGE_MMIO_CSR_IO_ADDR;
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localparam MMIO_CSR_MEM_ADDR = `AFU_IMAGE_MMIO_CSR_MEM_ADDR;
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localparam MMIO_CSR_DATA_SIZE = `AFU_IMAGE_MMIO_CSR_DATA_SIZE;
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logic [127:0] afu_id = `AFU_ACCEL_UUID;
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typedef enum logic[3:0] {
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STATE_IDLE,
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STATE_READ,
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STATE_WRITE,
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STATE_START,
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STATE_RUN,
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STATE_CLFLUSH
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} state_t;
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typedef logic [`LOG2UP(CCI_RD_WINDOW_SIZE)-1:0] t_cci_rdq_tag;
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typedef logic [$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:0] t_cci_rdq_data;
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state_t state;
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// Vortex ports ///////////////////////////////////////////////////////////////
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logic vx_dram_req_read;
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logic vx_dram_req_write;
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logic [DRAM_ADDR_WIDTH-1:0] vx_dram_req_addr;
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logic [DRAM_LINE_WIDTH-1:0] vx_dram_req_data;
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logic [DRAM_TAG_WIDTH-1:0] vx_dram_req_tag;
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logic vx_dram_req_ready;
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logic vx_dram_rsp_valid;
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logic [DRAM_LINE_WIDTH-1:0] vx_dram_rsp_data;
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logic [DRAM_TAG_WIDTH-1:0] vx_dram_rsp_tag;
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logic vx_dram_rsp_ready;
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logic vx_snp_req_valid;
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logic [DRAM_ADDR_WIDTH-1:0] vx_snp_req_addr;
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logic vx_snp_req_ready;
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logic vx_busy;
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// AVS Queues /////////////////////////////////////////////////////////////////
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logic avs_rtq_push;
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logic [DRAM_TAG_WIDTH-1:0] avs_rtq_din;
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logic avs_rtq_pop;
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logic [DRAM_TAG_WIDTH-1:0] avs_rtq_dout;
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logic avs_rtq_empty;
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logic avs_rtq_full;
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logic avs_rdq_push;
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t_local_mem_data avs_rdq_din;
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logic avs_rdq_pop;
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t_local_mem_data avs_rdq_dout;
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logic avs_rdq_empty;
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logic avs_rdq_full;
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// CSR variables //////////////////////////////////////////////////////////////
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logic [2:0] csr_cmd;
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t_ccip_clAddr csr_io_addr;
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t_local_mem_addr csr_mem_addr;
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logic [DRAM_ADDR_WIDTH-1:0] csr_data_size;
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// MMIO controller ////////////////////////////////////////////////////////////
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t_ccip_c0_ReqMmioHdr mmioHdr;
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always_comb
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begin
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mmioHdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr);
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end
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always_ff @(posedge clk)
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begin
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if (SoftReset) begin
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af2cp_sTxPort.c2.hdr <= 0;
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af2cp_sTxPort.c2.data <= 0;
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af2cp_sTxPort.c2.mmioRdValid <= 0;
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csr_cmd <= 0;
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csr_io_addr <= 0;
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csr_mem_addr <= 0;
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csr_data_size <= 0;
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end
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else begin
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csr_cmd <= 0;
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af2cp_sTxPort.c2.mmioRdValid <= 0;
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// serve MMIO write request
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if (cp2af_sRxPort.c0.mmioWrValid)
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begin
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case (mmioHdr.address)
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MMIO_CSR_IO_ADDR: begin
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csr_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data);
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$display("%t: CSR_IO_ADDR: 0x%h", $time, t_ccip_clAddr'(cp2af_sRxPort.c0.data));
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end
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MMIO_CSR_MEM_ADDR: begin
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csr_mem_addr <= t_local_mem_addr'(cp2af_sRxPort.c0.data);
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$display("%t: CSR_MEM_ADDR: 0x%h", $time, t_local_mem_addr'(cp2af_sRxPort.c0.data));
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end
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MMIO_CSR_DATA_SIZE: begin
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csr_data_size <= $bits(csr_data_size)'(cp2af_sRxPort.c0.data);
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$display("%t: CSR_DATA_SIZE: %0d", $time, $bits(csr_data_size)'(cp2af_sRxPort.c0.data));
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end
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MMIO_CSR_CMD: begin
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csr_cmd <= $bits(csr_cmd)'(cp2af_sRxPort.c0.data);
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$display("%t: CSR_CMD: %0d", $time, $bits(csr_cmd)'(cp2af_sRxPort.c0.data));
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end
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default: begin
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// user-defined CSRs
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//if (mmioHdr.addres >= MMIO_CSR_USER) begin
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// write Vortex CRS
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//end
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end
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endcase
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end
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// serve MMIO read requests
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if (cp2af_sRxPort.c0.mmioRdValid) begin
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af2cp_sTxPort.c2.hdr.tid <= mmioHdr.tid; // copy TID
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case (mmioHdr.address)
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// AFU header
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16'h0000: af2cp_sTxPort.c2.data <= {
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4'b0001, // Feature type = AFU
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8'b0, // reserved
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4'b0, // afu minor revision = 0
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7'b0, // reserved
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1'b1, // end of DFH list = 1
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24'b0, // next DFH offset = 0
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4'b0, // afu major revision = 0
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12'b0 // feature ID = 0
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};
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AFU_ID_L: af2cp_sTxPort.c2.data <= afu_id[63:0]; // afu id low
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AFU_ID_H: af2cp_sTxPort.c2.data <= afu_id[127:64]; // afu id hi
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16'h0006: af2cp_sTxPort.c2.data <= 64'h0; // next AFU
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16'h0008: af2cp_sTxPort.c2.data <= 64'h0; // reserved
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MMIO_CSR_STATUS: begin
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if (state != af2cp_sTxPort.c2.data) begin
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$display("%t: STATUS: state=%0d", $time, state);
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end
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af2cp_sTxPort.c2.data <= state;
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end
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default: af2cp_sTxPort.c2.data <= 64'h0;
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endcase
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af2cp_sTxPort.c2.mmioRdValid <= 1; // post response
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end
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end
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end
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// COMMAND FSM ////////////////////////////////////////////////////////////////
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logic [DRAM_ADDR_WIDTH-1:0] cci_write_ctr;
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logic [DRAM_ADDR_WIDTH-1:0] avs_read_ctr;
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logic [DRAM_ADDR_WIDTH-1:0] avs_write_ctr;
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logic [DRAM_ADDR_WIDTH-1:0] snp_req_ctr;
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logic [9:0] snp_req_delay;
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logic vx_reset;
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always_ff @(posedge clk)
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begin
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if (SoftReset) begin
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state <= STATE_IDLE;
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vx_reset <= 0;
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end
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else begin
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vx_reset <= 0;
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case (state)
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STATE_IDLE: begin
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case (csr_cmd)
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CMD_TYPE_READ: begin
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$display("%t: STATE READ: ia=%h da=%h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size);
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state <= STATE_READ;
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end
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CMD_TYPE_WRITE: begin
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$display("%t: STATE WRITE: ia=%h da=%h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size);
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state <= STATE_WRITE;
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end
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CMD_TYPE_RUN: begin
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$display("%t: STATE START", $time);
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vx_reset <= 1;
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state <= STATE_START;
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end
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CMD_TYPE_CLFLUSH: begin
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$display("%t: STATE CFLUSH: da=%h sz=%0d", $time, csr_mem_addr, csr_data_size);
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state <= STATE_CLFLUSH;
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end
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endcase
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end
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STATE_READ: begin
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if (cci_write_ctr >= csr_data_size) begin
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state <= STATE_IDLE;
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end
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end
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STATE_WRITE: begin
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if (avs_write_ctr >= csr_data_size) begin
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state <= STATE_IDLE;
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end
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end
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STATE_START: begin // vortex reset cycle
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state <= STATE_RUN;
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end
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STATE_RUN: begin
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if (!vx_busy) begin
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state <= STATE_IDLE;
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end
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end
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STATE_CLFLUSH: begin
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if (snp_req_delay >= VX_SNOOP_DELAY) begin
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state <= STATE_IDLE;
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end
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end
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endcase
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end
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end
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// AVS Controller /////////////////////////////////////////////////////////////
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logic cci_rdq_empty;
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t_cci_rdq_data cci_rdq_dout;
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logic cci_rdq_pop;
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logic [DRAM_TAG_WIDTH-1:0] dram_req_tag;
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t_ccip_clAddr next_avs_address;
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always_comb
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begin
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next_avs_address = csr_mem_addr + {avs_write_ctr[DRAM_ADDR_WIDTH-1:$bits(t_cci_rdq_tag)], t_cci_rdq_tag'(cci_rdq_dout)};
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cci_rdq_pop = (state == STATE_WRITE
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&& !cci_rdq_empty
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&& !avs_waitrequest
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&& avs_write_ctr < csr_data_size);
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end
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always_ff @(posedge clk)
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begin
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if (SoftReset)
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begin
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mem_bank_select <= 0;
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avs_burstcount <= 1;
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avs_byteenable <= 64'hffffffffffffffff;
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avs_read <= 0;
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avs_write <= 0;
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avs_read_ctr <= 0;
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avs_write_ctr <= 0;
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end
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else begin
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avs_read <= 0;
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avs_write <= 0;
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case (state)
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STATE_IDLE: begin
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avs_read_ctr <= 0;
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avs_write_ctr <= 0;
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end
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STATE_READ: begin
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if (!avs_rtq_full
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&& !avs_rdq_full
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&& !avs_waitrequest
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&& avs_read_ctr < csr_data_size)
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begin
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avs_address <= csr_mem_addr + avs_read_ctr;
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avs_read_ctr <= avs_read_ctr + 1;
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avs_read <= 1;
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$display("%t: AVS Rd Req: addr=%h", $time, csr_mem_addr + avs_read_ctr);
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end
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end
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STATE_WRITE: begin
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if (cci_rdq_pop)
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begin
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avs_writedata <= cci_rdq_dout[$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:$bits(t_cci_rdq_tag)];
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avs_address <= next_avs_address;
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avs_write_ctr <= avs_write_ctr + 1;
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avs_write <= 1;
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$display("%t: AVS Wr Req: addr=%h (%0d/%0d)", $time, next_avs_address, avs_write_ctr + 1, csr_data_size);
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end
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end
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STATE_RUN, STATE_CLFLUSH: begin
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if (vx_dram_req_read
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&& vx_dram_req_ready)
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begin
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avs_address <= vx_dram_req_addr;
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dram_req_tag <= vx_dram_req_tag;
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avs_read <= 1;
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$display("%t: AVS Rd Req: addr=%h", $time, vx_dram_req_addr);
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end
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if (vx_dram_req_write
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&& vx_dram_req_ready)
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begin
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avs_address <= vx_dram_req_addr;
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avs_writedata <= vx_dram_req_data;
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avs_write <= 1;
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$display("%t: AVS Wr Req: addr=%h", $time, vx_dram_req_addr);
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end
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end
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endcase
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if (avs_readdatavalid)
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begin
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$display("%t: AVS Rd Rsp", $time);
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end
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end
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end
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// Vortex DRAM requests stalling
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logic vortex_enabled;
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always_comb
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begin
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vortex_enabled = (STATE_RUN == state) || (STATE_CLFLUSH == state);
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vx_dram_req_ready = vortex_enabled && !avs_waitrequest && !avs_rtq_full && !avs_rdq_full;
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end
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// Vortex DRAM fill response
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always_comb
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begin
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vx_dram_rsp_valid = vortex_enabled && !avs_rdq_empty;
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vx_dram_rsp_tag = avs_rtq_dout;
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vx_dram_rsp_data = avs_rdq_dout;
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end
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// AVS address read request queue /////////////////////////////////////////////
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logic cci_wr_req;
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always_comb
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begin
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avs_rtq_pop = vx_dram_rsp_valid || cci_wr_req;
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avs_rtq_din = dram_req_tag;
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avs_rtq_push = avs_read;
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end
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VX_generic_queue #(
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.DATAW(DRAM_TAG_WIDTH),
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.SIZE(AVS_RD_QUEUE_SIZE)
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) avs_rd_req_queue (
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.clk (clk),
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.reset (SoftReset),
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.push (avs_rtq_push),
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.data_in (avs_rtq_din),
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.pop (avs_rtq_pop),
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.data_out (avs_rtq_dout),
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.empty (avs_rtq_empty),
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.full (avs_rtq_full)
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);
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// AVS data read response queue ///////////////////////////////////////////////
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always_comb
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begin
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avs_rdq_pop = avs_rtq_pop;
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avs_rdq_din = avs_readdata;
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avs_rdq_push = avs_readdatavalid;
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end
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VX_generic_queue #(
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.DATAW(DRAM_LINE_WIDTH),
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.SIZE(AVS_RD_QUEUE_SIZE)
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) avs_rd_rsp_queue (
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.clk (clk),
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.reset (SoftReset),
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.push (avs_rdq_push),
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.data_in (avs_rdq_din),
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.pop (avs_rdq_pop),
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.data_out (avs_rdq_dout),
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.empty (avs_rdq_empty),
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.full (avs_rdq_full)
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);
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// CCI Read Request ///////////////////////////////////////////////////////////
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t_ccip_c0_ReqMemHdr cci_read_hdr;
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logic [DRAM_ADDR_WIDTH-1:0] cci_read_ctr;
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t_cci_rdq_tag cci_rdq_ctr;
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logic cci_rdq_full;
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logic cci_rdq_push;
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t_cci_rdq_data cci_rdq_din;
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logic cci_read_wait;
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always_comb
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begin
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cci_read_hdr = t_ccip_c0_ReqMemHdr'(0);
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cci_read_hdr.address = csr_io_addr + cci_read_ctr;
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cci_read_hdr.mdata = t_cci_rdq_tag'(cci_read_ctr);
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cci_rdq_push = (STATE_WRITE == state) && cp2af_sRxPort.c0.rspValid;
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cci_rdq_din = {cp2af_sRxPort.c0.data, t_cci_rdq_tag'(cp2af_sRxPort.c0.hdr.mdata)};
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end
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// Send read requests to CCI
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always_ff @(posedge clk)
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begin
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if (SoftReset) begin
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af2cp_sTxPort.c0.hdr <= 0;
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af2cp_sTxPort.c0.valid <= 0;
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cci_read_ctr <= 0;
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cci_rdq_ctr <= 0;
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cci_read_wait <= 0;
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end
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else begin
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af2cp_sTxPort.c0.valid <= 0;
|
|
|
|
if (STATE_IDLE == state) begin
|
|
cci_read_ctr <= 0;
|
|
cci_rdq_ctr <= 0;
|
|
cci_read_wait <= 0;
|
|
end
|
|
|
|
if (STATE_WRITE == state
|
|
&& !cp2af_sRxPort.c0TxAlmFull // ensure read queue not full
|
|
&& !cci_rdq_full // ensure destination queue not full
|
|
&& !cci_read_wait // ensure the last batch has arrived
|
|
&& cci_read_ctr < csr_data_size) // ensure not done
|
|
begin
|
|
af2cp_sTxPort.c0.hdr <= cci_read_hdr;
|
|
af2cp_sTxPort.c0.valid <= 1;
|
|
cci_read_ctr <= cci_read_ctr + 1;
|
|
if (cci_read_ctr == (CCI_RD_WINDOW_SIZE-1)) begin
|
|
cci_read_wait <= 1; // end current request batch
|
|
end
|
|
$display("%t: CCI Rd Req: addr=%h", $time, cci_read_hdr.address);
|
|
end
|
|
|
|
if (cci_rdq_push) begin
|
|
cci_rdq_ctr <= cci_rdq_ctr + 1;
|
|
if (cci_rdq_ctr == (CCI_RD_WINDOW_SIZE-1)) begin
|
|
cci_read_wait <= 0; // restart new request batch
|
|
end
|
|
$display("%t: CCI Rd Rsp: idx=%d, ctr=%d", $time, t_cci_rdq_tag'(cp2af_sRxPort.c0.hdr.mdata), cci_rdq_ctr);
|
|
end
|
|
end
|
|
end
|
|
|
|
VX_generic_queue #(
|
|
.DATAW($bits(t_ccip_clData) + $bits(t_cci_rdq_tag)),
|
|
.SIZE(CCI_RD_QUEUE_SIZE)
|
|
) cci_rd_req_queue (
|
|
.clk (clk),
|
|
.reset (SoftReset),
|
|
.push (cci_rdq_push),
|
|
.data_in (cci_rdq_din),
|
|
.pop (cci_rdq_pop),
|
|
.data_out (cci_rdq_dout),
|
|
.empty (cci_rdq_empty),
|
|
.full (cci_rdq_full)
|
|
);
|
|
|
|
// CCI Write Request //////////////////////////////////////////////////////////
|
|
|
|
t_ccip_c1_ReqMemHdr cci_write_hdr;
|
|
|
|
logic cci_write_wait;
|
|
|
|
always_comb
|
|
begin
|
|
cci_wr_req = (STATE_READ == state)
|
|
&& !avs_rdq_empty
|
|
&& !cp2af_sRxPort.c1TxAlmFull
|
|
&& !cci_write_wait
|
|
&& cci_write_ctr < csr_data_size;
|
|
|
|
cci_write_hdr = t_ccip_c1_ReqMemHdr'(0);
|
|
cci_write_hdr.address = csr_io_addr + cci_write_ctr;
|
|
cci_write_hdr.sop = 1; // single line write mode
|
|
end
|
|
|
|
// Send write requests to CCI
|
|
always_ff @(posedge clk)
|
|
begin
|
|
if (SoftReset) begin
|
|
af2cp_sTxPort.c1.hdr <= 0;
|
|
af2cp_sTxPort.c1.data <= 0;
|
|
af2cp_sTxPort.c1.valid <= 0;
|
|
cci_write_ctr <= 0;
|
|
cci_write_wait <= 0;
|
|
end
|
|
else begin
|
|
af2cp_sTxPort.c1.valid <= 0;
|
|
|
|
if (STATE_IDLE == state) begin
|
|
cci_write_ctr <= 0;
|
|
end
|
|
|
|
if (cci_wr_req) begin
|
|
af2cp_sTxPort.c1.hdr <= cci_write_hdr;
|
|
af2cp_sTxPort.c1.data <= t_ccip_clData'(avs_rdq_dout);
|
|
af2cp_sTxPort.c1.valid <= 1;
|
|
cci_write_wait <= 1;
|
|
$display("%t: CCI Wr Req: addr=%h", $time, cci_write_hdr.address);
|
|
end
|
|
|
|
if (cci_write_wait
|
|
&& cp2af_sRxPort.c1.rspValid)
|
|
begin
|
|
cci_write_ctr <= cci_write_ctr + 1;
|
|
cci_write_wait <= 0;
|
|
$display("%t: CCI Wr Rsp (%0d/%0d)", $time, cci_write_ctr + 1, csr_data_size);
|
|
end
|
|
end
|
|
end
|
|
|
|
// Vortex cache snooping //////////////////////////////////////////////////////
|
|
|
|
always_ff @(posedge clk)
|
|
begin
|
|
if (SoftReset) begin
|
|
vx_snp_req_valid <= 0;
|
|
snp_req_ctr <= 0;
|
|
snp_req_delay <= 0;
|
|
end
|
|
else begin
|
|
if (STATE_IDLE == state) begin
|
|
snp_req_ctr <= 0;
|
|
snp_req_delay <= 0;
|
|
end
|
|
|
|
vx_snp_req_valid <= 0;
|
|
|
|
if ((STATE_CLFLUSH == state)
|
|
&& (snp_req_ctr < csr_data_size)
|
|
&& vx_snp_req_ready)
|
|
begin
|
|
vx_snp_req_addr <= csr_mem_addr + snp_req_ctr;
|
|
vx_snp_req_valid <= 1;
|
|
snp_req_ctr <= snp_req_ctr + 1;
|
|
end
|
|
|
|
if (snp_req_ctr == csr_data_size) begin
|
|
snp_req_delay <= snp_req_delay + 1;
|
|
end
|
|
end
|
|
end
|
|
|
|
// Vortex binding /////////////////////////////////////////////////////////////
|
|
|
|
Vortex_Socket #() vx_socket (
|
|
.clk (clk),
|
|
.reset (vx_reset),
|
|
|
|
// DRAM request
|
|
.dram_req_write (vx_dram_req_write),
|
|
.dram_req_read (vx_dram_req_read),
|
|
.dram_req_addr (vx_dram_req_addr),
|
|
.dram_req_data (vx_dram_req_data),
|
|
.dram_req_tag (vx_dram_req_tag),
|
|
.dram_req_ready (vx_dram_req_ready),
|
|
|
|
// DRAM response
|
|
.dram_rsp_valid (vx_dram_rsp_valid),
|
|
.dram_rsp_data (vx_dram_rsp_data),
|
|
.dram_rsp_tag (vx_dram_rsp_tag),
|
|
.dram_rsp_ready (vx_dram_rsp_ready),
|
|
|
|
// Cache snooping
|
|
.snp_req_valid (vx_snp_req_valid),
|
|
.snp_req_addr (vx_snp_req_addr),
|
|
.snp_req_ready (vx_snp_req_ready),
|
|
|
|
// I/O request
|
|
.io_req_read (),
|
|
.io_req_write (),
|
|
.io_req_addr (),
|
|
.io_req_data (),
|
|
.io_req_byteen (),
|
|
.io_req_tag (),
|
|
.io_req_ready (0),
|
|
|
|
// I/O response
|
|
.io_rsp_valid (0),
|
|
.io_rsp_data (0),
|
|
.io_rsp_tag (0),
|
|
.io_rsp_ready (),
|
|
|
|
// status
|
|
.busy (vx_busy),
|
|
.ebreak ()
|
|
);
|
|
|
|
endmodule
|