Blaise Tine 3f5fd6d394 using shiftreg-based skid buffers

2021-02-28 02:20:09 -08:00

..

configs

project directories reorganization

2020-04-14 06:35:20 -04:00

dpi

speeding up simulation using dedicated full dpi-based FPU core

2021-01-06 18:44:06 -08:00

models/memory

RTL code refactoring

2020-04-19 03:38:00 -04:00

modelsim

yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

rtl

using shiftreg-based skid buffers

2021-02-28 02:20:09 -08:00

scripts

cache bank refactoring - removing unecessary core response fifo & restoring single port data access

2021-02-21 21:47:46 -08:00

simulate

moving MUL unit into ALU unit

2021-02-23 13:49:02 -08:00

syn

cache bank refactoring - removing unecessary core response fifo & restoring single port data access

2021-02-21 21:47:46 -08:00

unit_tests

simX refactoring + removed oldRTL + CSR updates

2021-02-06 12:52:54 -08:00

.gitignore

adding dram writeenable support + scheduler bug fixes

2020-05-27 19:00:23 -04:00

Makefile

scope refactoring

2020-10-03 18:53:21 -04:00