d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
134 lines
3.2 KiB
Bash
Executable File
134 lines
3.2 KiB
Bash
Executable File
#!/bin/bash
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# this script uses sv2v and yosys tools to run.
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# sv2v: https://github.com/zachjs/sv2v
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# yosys: http://www.clifford.at/yosys/
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# exit when any command fails
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set -e
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source=""
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top_level=""
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dir_list=()
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inc_args=""
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macro_args=""
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no_warnings=1
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process="elaborate,netlist,techmap,verilog"
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declare -a excluded_warnings=("Resizing cell port")
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is_excluded_warning() {
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local warning_text="$1"
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for exclusion in "${excluded_warnings[@]}"; do
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if [[ "$warning_text" == *"$exclusion"* ]]; then
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return $no_warnings
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fi
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done
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return 1
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}
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checkErrors()
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{
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log_file="$1"
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if grep -q "Error: " "$log_file"; then
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echo "Error: found errors during synthesis!"
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exit 1
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fi
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count=0
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while IFS= read -r line; do
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if [[ "$line" == *"Warning:"* ]]; then
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warning_text="${line#Warning: }"
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if ! is_excluded_warning "$warning_text"; then
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count=$(expr $count + 1)
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fi
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fi
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done < $log_file
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if [ "$count" -ne 0 ]; then
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echo "Error: found $count unexpected warnings during synthesis!"
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exit $count
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fi
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}
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usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; }
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[ $# -eq 0 ] && usage
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while getopts "s:t:I:D:P:Wh" arg; do
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case $arg in
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s) # source
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source=${OPTARG}
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;;
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t) # top-level
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top_level=${OPTARG}
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;;
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I) # include directory
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dir_list+=(${OPTARG})
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inc_args="$inc_args -I${OPTARG}"
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;;
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D) # macro definition
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macro_args="$macro_args -D${OPTARG}"
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;;
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P) # process
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process=${OPTARG}
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;;
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W) # allow warnings
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no_warnings=0
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;;
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h | *)
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usage
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exit 0
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;;
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esac
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done
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{
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# read design sources
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for dir in "${dir_list[@]}"
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do
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for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f)
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do
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echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $file"
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done
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done
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if [ -n "$source" ]; then
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echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $source"
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fi
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# elaborate
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if echo "$process" | grep -q "elaborate"; then
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echo "hierarchy -top $top_level"
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fi
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# convert to netlist
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if echo "$process" | grep -q "netlist"; then
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echo "proc; opt"
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fi
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# convert to gate logic
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if echo "$process" | grep -q "techmap"; then
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echo "techmap; opt"
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fi
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# write synthesized design
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if echo "$process" | grep -q "verilog"; then
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echo "write_verilog synth.v"
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fi
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} > synth.ys
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yosys -l yosys.log synth.ys
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checkErrors yosys.log
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