70 lines
2.7 KiB
Verilog
70 lines
2.7 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_dram_arb #(
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parameter BANK_LINE_SIZE = 1,
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parameter NUM_REQUESTS = 1,
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parameter CORE_TAG_WIDTH = 1,
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parameter DRAM_TAG_WIDTH = 1
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) (
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input wire clk,
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input wire reset,
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// Core request
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input wire [NUM_REQUESTS-1:0] core_req_read,
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input wire [NUM_REQUESTS-1:0] core_req_write,
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input wire [NUM_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] core_req_addr,
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input wire [NUM_REQUESTS-1:0][`BANK_LINE_WIDTH-1:0] core_req_data,
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input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
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output wire [NUM_REQUESTS-1:0] core_req_ready,
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// Core response
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output wire [NUM_REQUESTS-1:0] core_rsp_valid,
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output wire [NUM_REQUESTS-1:0][`BANK_LINE_WIDTH-1:0]core_rsp_data,
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output wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
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input wire [NUM_REQUESTS-1:0] core_rsp_ready,
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// DRAM request
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output wire dram_req_read,
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output wire dram_req_write,
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output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
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output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
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input wire dram_req_ready,
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// DRAM response
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input wire dram_rsp_valid,
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input wire [`BANK_LINE_WIDTH-1:0] dram_rsp_data,
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input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
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output wire dram_rsp_ready
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);
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reg [`REQS_BITS-1:0] bus_req_sel;
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always @(posedge clk) begin
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if (reset) begin
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bus_req_sel <= 0;
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end else begin
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bus_req_sel <= bus_req_sel + 1;
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end
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end
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assign dram_req_read = core_req_read [bus_req_sel];
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assign dram_req_write = core_req_write [bus_req_sel];
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assign dram_req_addr = core_req_addr [bus_req_sel];
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assign dram_req_data = core_req_data [bus_req_sel];
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assign dram_req_tag = {core_req_tag [bus_req_sel], (`REQS_BITS)'(bus_req_sel)};
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign core_req_ready[i] = dram_req_ready && (bus_req_sel == `REQS_BITS'(i));
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end
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wire [`REQS_BITS-1:0] bus_rsp_sel = dram_rsp_tag[`REQS_BITS-1:0];
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genvar i;
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign core_rsp_valid[i] = dram_rsp_valid && (bus_rsp_sel == `REQS_BITS'(i));
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assign core_rsp_data[i] = dram_rsp_data;
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assign core_rsp_tag[i] = dram_rsp_tag[`REQS_BITS +: CORE_TAG_WIDTH];
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end
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assign dram_rsp_ready = core_rsp_ready[bus_rsp_sel];
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endmodule |