38 lines
659 B
Verilog
38 lines
659 B
Verilog
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`include "VX_define.v"
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// Old SM file
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module VX_shared_memory(
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input wire clk,
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input wire[31:0] in_address[`NT_M1:0],
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input wire[2:0] in_mem_read,
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input wire[2:0] in_mem_write,
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input wire in_valid[`NT_M1:0],
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input wire[31:0] in_data[`NT_M1:0],
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output reg[31:0] out_data[`NT_M1:0]
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);
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reg[31:0] mem[255:0]; // 2^2 * 2^8 = 2^10 = 1kb of memory
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always @(posedge clk)
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begin
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if ((in_mem_write == `SW_MEM_WRITE) && in_valid)
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begin
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mem[in_address[0][9:2]] <= in_data;
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end
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if (in_mem_read == `LW_MEM_READ)
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begin
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assign out_data[0] = mem[in_address[0][9:2]];
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end
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end
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endmodule // VX_shared_memory
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