404 lines
16 KiB
Verilog
404 lines
16 KiB
Verilog
`include "VX_cache_config.v"
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module VX_bank (
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input wire clk,
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input wire reset,
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// Input Core Request
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input wire delay_req,
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input wire [`NUMBER_REQUESTS-1:0] bank_valids,
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input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr,
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input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata,
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input wire [4:0] bank_rd,
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input wire [1:0] bank_wb,
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input wire [`NW_M1:0] bank_warp_num,
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input wire [2:0] bank_mem_read,
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input wire [2:0] bank_mem_write,
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output wire reqq_full,
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// Output Core WB
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input wire bank_wb_pop,
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output wire bank_wb_valid,
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output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] bank_wb_tid,
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output wire [4:0] bank_wb_rd,
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output wire [1:0] bank_wb_wb,
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output wire [`NW_M1:0] bank_wb_warp_num,
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output wire [31:0] bank_wb_data,
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// Dram Fill Requests
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output wire dram_fill_req,
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output wire[31:0] dram_fill_req_addr,
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input wire dram_fill_req_queue_full,
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// Dram Fill Response
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_addr,
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input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
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output wire dram_fill_accept,
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// Dram WB Requests
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input wire dram_wb_queue_pop,
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output wire dram_wb_req,
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output wire[31:0] dram_wb_req_addr,
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output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data
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);
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wire dfpq_pop;
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wire dfpq_empty;
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wire dfpq_full;
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wire[31:0] dfpq_addr_st0;
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wire[`BANK_LINE_SIZE_RNG][31:0] dfpq_filldata_st0;
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reg dfpq_hazard_st0;
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assign dram_fill_accept = !dfpq_full;
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VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
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.clk (clk),
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.reset (reset),
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.push (dram_fill_rsp),
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.in_data ({dram_fill_addr, dram_fill_rsp_data}),
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.pop (dfpq_pop),
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.out_data({dfpq_addr_st0, dfpq_filldata_st0}),
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.empty (dfpq_empty),
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.full (dfpq_full)
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);
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wire reqq_pop;
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wire reqq_push;
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wire reqq_empty;
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wire reqq_req_st0;
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wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] reqq_req_tid_st0;
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wire [31:0] reqq_req_addr_st0;
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wire [31:0] reqq_req_writeword_st0;
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wire [4:0] reqq_req_rd_st0;
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wire [1:0] reqq_req_wb_st0;
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wire [`NW_M1:0] reqq_req_warp_num_st0;
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wire [2:0] reqq_req_mem_read_st0;
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wire [2:0] reqq_req_mem_write_st0;
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reg reqq_hazard_st0;
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assign reqq_push = !delay_req && (|bank_valids);
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VX_cache_req_queue req_queue(
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.clk (clk),
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.reset (reset),
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// Enqueue
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.reqq_push (reqq_push),
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.bank_valids (bank_valids),
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.bank_addr (bank_addr),
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.bank_writedata (bank_writedata),
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.bank_rd (bank_rd),
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.bank_wb (bank_wb),
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.bank_warp_num (bank_warp_num),
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.bank_mem_read (bank_mem_read),
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.bank_mem_write (bank_mem_write),
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// Dequeue
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.reqq_pop (reqq_pop),
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.reqq_req_st0 (reqq_req_st0),
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.reqq_req_tid_st0 (reqq_req_tid_st0),
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.reqq_req_addr_st0 (reqq_req_addr_st0),
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.reqq_req_writedata_st0(reqq_req_writeword_st0),
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.reqq_req_rd_st0 (reqq_req_rd_st0),
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.reqq_req_wb_st0 (reqq_req_wb_st0),
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.reqq_req_warp_num_st0 (reqq_req_warp_num_st0),
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.reqq_req_mem_read_st0 (reqq_req_mem_read_st0),
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.reqq_req_mem_write_st0(reqq_req_mem_write_st0),
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.reqq_empty (reqq_empty),
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.reqq_full (reqq_full)
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);
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wire mrvq_pop;
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wire mrvq_full;
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wire mrvq_valid_st0;
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wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] mrvq_tid_st0;
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wire [31:0] mrvq_addr_st0;
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wire [31:0] mrvq_writeword_st0;
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wire [4:0] mrvq_rd_st0;
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wire [1:0] mrvq_wb_st0;
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wire [`NW_M1:0] mrvq_warp_num_st0;
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wire [2:0] mrvq_mem_read_st0;
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wire [2:0] mrvq_mem_write_st0;
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reg mrvq_hazard_st0;
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wire miss_add;
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wire[31:0] miss_add_addr;
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wire[31:0] miss_add_data;
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wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] miss_add_tid;
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wire[4:0] miss_add_rd;
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wire[1:0] miss_add_wb;
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wire[`NW_M1:0] miss_add_warp_num;
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wire[2:0] miss_add_mem_read;
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wire[2:0] miss_add_mem_write;
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VX_cache_miss_resrv mrvq_queue(
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.clk (clk),
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.reset (reset),
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// Enqueue
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.miss_add (miss_add), // Need to do all
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.miss_add_addr (miss_add_addr),
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.miss_add_data (miss_add_data),
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.miss_add_tid (miss_add_tid),
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.miss_add_rd (miss_add_rd),
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.miss_add_wb (miss_add_wb),
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.miss_add_warp_num (miss_add_warp_num),
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.miss_add_mem_read (miss_add_mem_read),
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.miss_add_mem_write (miss_add_mem_write),
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.miss_resrv_full (mrvq_full),
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// Broadcast
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.is_fill_st1 (is_fill_st2),
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.fill_addr_st1 (addr_st2),
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// Dequeue
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.miss_resrv_pop (mrvq_pop),
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.miss_resrv_valid_st0 (mrvq_valid_st0),
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.miss_resrv_addr_st0 (mrvq_addr_st0),
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.miss_resrv_data_st0 (mrvq_writeword_st0),
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.miss_resrv_tid_st0 (mrvq_tid_st0),
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.miss_resrv_rd_st0 (mrvq_rd_st0),
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.miss_resrv_wb_st0 (mrvq_wb_st0),
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.miss_resrv_warp_num_st0 (mrvq_warp_num_st0),
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.miss_resrv_mem_read_st0 (mrvq_mem_read_st0),
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.miss_resrv_mem_write_st0(mrvq_mem_write_st0)
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);
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wire stall_bank_pipe;
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assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0;
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assign mrvq_pop = !dfpq_pop && mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0;
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assign reqq_pop = !mrvq_pop && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !reqq_hazard_st0;
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integer st1_cycle;
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always @(*) begin
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assign dfpq_hazard_st0 = 0;
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assign mrvq_hazard_st0 = 0;
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assign reqq_hazard_st0 = 0;
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for (st1_cycle = 0; st1_cycle < `STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin
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if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin
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if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign dfpq_hazard_st0 = 1;
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if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign mrvq_hazard_st0 = 1;
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if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign reqq_hazard_st0 = 1;
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end
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end
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end
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wire qual_is_fill_st0;
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wire qual_valid_st0;
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wire [31:0] qual_addr_st0;
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wire [31:0] qual_writeword_st0;
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wire [`BANK_LINE_SIZE_RNG][31:0] qual_writedata_st0;
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wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0;
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wire qual_going_to_write_st0;
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wire valid_st1 [`STAGE_1_CYCLES-1:0];
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wire going_to_write_st1[`STAGE_1_CYCLES-1:0];
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wire [31:0] addr_st1 [`STAGE_1_CYCLES-1:0];
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wire [31:0] writeword_st1 [`STAGE_1_CYCLES-1:0];
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wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [`STAGE_1_CYCLES-1:0];
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wire is_fill_st1 [`STAGE_1_CYCLES-1:0];
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wire [`BANK_LINE_SIZE_RNG][31:0] writedata_st1 [`STAGE_1_CYCLES-1:0];
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assign qual_is_fill_st0 = dfpq_pop;
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assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop;
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assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 :
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mrvq_pop ? mrvq_addr_st0 :
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reqq_pop ? reqq_req_addr_st0 :
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0;
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assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 :
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reqq_pop ? reqq_req_writeword_st0 :
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0;
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assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 0;
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assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0 , mrvq_wb_st0 , mrvq_warp_num_st0 , mrvq_mem_read_st0 , mrvq_mem_write_st0 , mrvq_tid_st0 } :
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reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
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0;
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assign qual_going_to_write_st0 = dfpq_pop ? 1 :
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(mrvq_pop && (mrvq_mem_write_st0 != `NO_MEM_WRITE)) ? 1 :
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(reqq_pop && (reqq_req_mem_write_st0 != `NO_MEM_WRITE)) ? 1 :
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0;
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VX_generic_register #(.N( 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_c0 (
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.clk (clk),
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.reset(reset),
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.stall(stall_bank_pipe),
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.flush(0),
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.in ({qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}),
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.out ({going_to_write_st1[0] , valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0]})
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);
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genvar curr_stage;
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generate
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for (curr_stage = 1; curr_stage < `STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin
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VX_generic_register #(.N( 1 + 1 + 32 + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*32) + 1)) s0_1_cc (
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.clk (clk),
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.reset(reset),
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.stall(stall_bank_pipe),
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.flush(0),
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.in ({going_to_write_st1[curr_stage-1], valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1]}),
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.out ({going_to_write_st1[curr_stage] , valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] })
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);
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end
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endgenerate
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wire[31:0] readword_st1e;
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wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st1e;
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wire[`TAG_SELECT_SIZE_RNG] readtag_st1e;
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wire miss_st1e;
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wire dirty_st1e;
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wire [4:0] rd_st1e;
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wire [1:0] wb_st1e;
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wire [`NW_M1:0] warp_num_st1e;
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wire [2:0] mem_read_st1e;
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wire [2:0] mem_write_st1e;
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wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] tid_st1e;
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wire fill_saw_dirty_st1e;
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assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[`STAGE_1_CYCLES-1];
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VX_tag_data_access VX_tag_data_access(
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.clk (clk),
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.reset (reset),
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.stall (stall_bank_pipe),
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// Initial Read
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.readaddr_st10 (addr_st1[0]),
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// Actual Read/Write
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.valid_req_st1e(valid_st1[`STAGE_1_CYCLES-1]),
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.writefill_st1e(is_fill_st1[`STAGE_1_CYCLES-1]),
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.writeaddr_st1e(addr_st1[`STAGE_1_CYCLES-1]),
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.writeword_st1e(writeword_st1[`STAGE_1_CYCLES-1]),
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.writedata_st1e(writedata_st1[`STAGE_1_CYCLES-1]),
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.mem_write_st1e(mem_write_st1e),
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.mem_read_st1e (mem_read_st1e),
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// Read Data
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.readword_st1e (readword_st1e),
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.readdata_st1e (readdata_st1e),
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.readtag_st1e (readtag_st1e),
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.miss_st1e (miss_st1e),
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.dirty_st1e (dirty_st1e),
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.fill_saw_dirty_st1e(fill_saw_dirty_st1e)
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);
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wire qual_valid_st1e_2 = valid_st1[`STAGE_1_CYCLES-1] && !is_fill_st1[`STAGE_1_CYCLES-1];
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wire valid_st2;
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wire[31:0] addr_st2;
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wire[31:0] writeword_st2;
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wire[31:0] readword_st2;
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wire[`BANK_LINE_SIZE_RNG][31:0] readdata_st2;
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wire miss_st2;
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wire dirty_st2;
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wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
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wire[`TAG_SELECT_SIZE_RNG] readtag_st2;
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wire is_fill_st2;
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wire fill_saw_dirty_st2;
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VX_generic_register #(.N( 1 + 1 + 1 + 32 + 32 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1 + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS)) st_1e_2 (
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.clk (clk),
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.reset(reset),
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.stall(stall_bank_pipe),
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.flush(0),
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.in ({fill_saw_dirty_st1e, is_fill_st1[`STAGE_1_CYCLES-1], qual_valid_st1e_2, addr_st1[`STAGE_1_CYCLES-1], writeword_st1[`STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[`STAGE_1_CYCLES-1]}),
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.out ({fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
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);
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// Enqueue to miss reserv if it's a valid miss
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assign miss_add = valid_st2 && miss_st2;
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assign miss_add_addr = addr_st2;
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assign miss_add_data = writeword_st2;
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assign {miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
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// Enqueue to CWB Queue
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wire cwbq_push = valid_st2 && !miss_st2;
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wire [31:0] cwbq_data = readword_st2;
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wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
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wire [4:0] cwbq_rd = miss_add_rd;
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wire [1:0] cwbq_wb = miss_add_wb;
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wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num;
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wire cwbq_full;
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wire cwbq_empty;
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assign bank_wb_valid = !cwbq_empty;
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VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
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.clk (clk),
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.reset (reset),
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.push (cwbq_push),
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.in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data}),
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.pop (bank_wb_pop),
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.out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data}),
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.empty (cwbq_empty),
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.full (cwbq_full)
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);
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// Enqueue to DWB Queue
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wire dwbq_push = (valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2;
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wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]};
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wire[`BANK_LINE_SIZE_RNG][31:0] dwbq_req_data = readdata_st2;
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wire dwbq_empty;
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wire dwbq_full;
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wire invalidate_fill;
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wire possible_fill = valid_st2 && miss_st2;
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VX_fill_invalidator VX_fill_invalidator(
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.clk (clk),
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.reset (reset),
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.possible_fill (possible_fill),
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.success_fill (is_fill_st2),
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.fill_addr (addr_st2),
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.invalidate_fill (invalidate_fill)
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);
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// Enqueu in dram_fill_req
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assign dram_fill_req = valid_st2 && miss_st2 && !invalidate_fill;
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assign dram_fill_req_addr = addr_st2;
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assign dram_wb_req = !dwbq_empty;
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VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
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.clk (clk),
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.reset (reset),
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.push (dwbq_push),
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.in_data ({dwbq_req_addr, dwbq_req_data}),
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.pop (dram_wb_queue_pop),
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.out_data({dram_wb_req_addr, dram_wb_req_data}),
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.empty (dwbq_empty),
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.full (dwbq_full)
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);
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assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full);
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endmodule
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