c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
596 lines
23 KiB
Systemverilog
596 lines
23 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_cache_define.vh"
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module VX_cache import VX_gpu_pkg::*; #(
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parameter `STRING INSTANCE_ID = "",
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// Number of Word requests per cycle
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parameter NUM_REQS = 4,
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// Size of cache in bytes
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parameter CACHE_SIZE = 4096,
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// Size of line inside a bank in bytes
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parameter LINE_SIZE = 64,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Number of associative ways
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parameter NUM_WAYS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = `XLEN/8,
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// Core Response Queue Size
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parameter CRSQ_SIZE = 2,
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// Miss Reserv Queue Knob
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parameter MSHR_SIZE = 8,
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// Memory Response Queue Size
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parameter MRSQ_SIZE = 0,
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// Memory Request Queue Size
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parameter MREQ_SIZE = 4,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Request debug identifier
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parameter UUID_WIDTH = 0,
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// core request tag size
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parameter TAG_WIDTH = UUID_WIDTH + 1,
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// Core response output register
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parameter CORE_OUT_REG = 0,
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// Memory request output register
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parameter MEM_OUT_REG = 0
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) (
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// PERF
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`ifdef PERF_ENABLE
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output cache_perf_t cache_perf,
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`endif
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input wire clk,
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input wire reset,
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VX_mem_bus_if.slave core_bus_if [NUM_REQS],
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VX_mem_bus_if.master mem_bus_if
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);
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`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid parameter"))
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`STATIC_ASSERT(NUM_BANKS == (1 << `CLOG2(NUM_BANKS)), ("invalid parameter"))
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localparam REQ_SEL_WIDTH = `UP(`CS_REQ_SEL_BITS);
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localparam WORD_SEL_WIDTH = `UP(`CS_WORD_SEL_BITS);
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localparam MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE);
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localparam MEM_TAG_WIDTH = MSHR_ADDR_WIDTH + `CS_BANK_SEL_BITS;
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localparam WORDS_PER_LINE = LINE_SIZE / WORD_SIZE;
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localparam WORD_WIDTH = WORD_SIZE * 8;
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localparam WORD_SEL_BITS = `CLOG2(WORDS_PER_LINE);
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localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS);
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localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS);
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localparam LINE_ADDR_WIDTH = (`CS_WORD_ADDR_WIDTH - BANK_SEL_BITS - WORD_SEL_BITS);
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localparam CORE_REQ_DATAW = LINE_ADDR_WIDTH + 1 + WORD_SEL_WIDTH + WORD_SIZE + WORD_WIDTH + TAG_WIDTH;
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localparam CORE_RSP_DATAW = WORD_WIDTH + TAG_WIDTH;
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localparam CORE_REQ_BUF_ENABLE = (NUM_BANKS != 1) || (NUM_REQS != 1);
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localparam MEM_REQ_BUF_ENABLE = (NUM_BANKS != 1);
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`ifdef PERF_ENABLE
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wire [NUM_BANKS-1:0] perf_read_miss_per_bank;
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wire [NUM_BANKS-1:0] perf_write_miss_per_bank;
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wire [NUM_BANKS-1:0] perf_mshr_stall_per_bank;
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`endif
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wire [NUM_REQS-1:0] core_req_valid;
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wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr;
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wire [NUM_REQS-1:0] core_req_rw;
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wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen;
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wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data;
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wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_req_tag;
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wire [NUM_REQS-1:0] core_req_ready;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_req_valid[i] = core_bus_if[i].req_valid;
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assign core_req_addr[i] = core_bus_if[i].req_data.addr;
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assign core_req_rw[i] = core_bus_if[i].req_data.rw;
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assign core_req_byteen[i] = core_bus_if[i].req_data.byteen;
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assign core_req_data[i] = core_bus_if[i].req_data.data;
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assign core_req_tag[i] = core_bus_if[i].req_data.tag;
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assign core_bus_if[i].req_ready = core_req_ready[i];
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end
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///////////////////////////////////////////////////////////////////////////
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// Core response buffering
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wire [NUM_REQS-1:0] core_rsp_valid_s;
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wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data_s;
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wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s;
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wire [NUM_REQS-1:0] core_rsp_ready_s;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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`RESET_RELAY (core_rsp_reset, reset);
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VX_elastic_buffer #(
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.DATAW (`CS_WORD_WIDTH + TAG_WIDTH),
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.SIZE (CORE_REQ_BUF_ENABLE ? `OUT_REG_TO_EB_SIZE(CORE_OUT_REG) : 0),
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.OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG))
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) core_rsp_buf (
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.clk (clk),
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.reset (core_rsp_reset),
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.valid_in (core_rsp_valid_s[i]),
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.ready_in (core_rsp_ready_s[i]),
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.data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}),
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.data_out ({core_bus_if[i].rsp_data.data, core_bus_if[i].rsp_data.tag}),
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.valid_out (core_bus_if[i].rsp_valid),
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.ready_out (core_bus_if[i].rsp_ready)
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);
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end
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///////////////////////////////////////////////////////////////////////////
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// Memory request buffering
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wire mem_req_valid_s;
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wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr_s;
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wire mem_req_rw_s;
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wire [LINE_SIZE-1:0] mem_req_byteen_s;
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wire [`CS_LINE_WIDTH-1:0] mem_req_data_s;
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wire [MEM_TAG_WIDTH-1:0] mem_req_tag_s;
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wire mem_req_ready_s;
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`RESET_RELAY (mem_req_buf_reset, reset);
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VX_elastic_buffer #(
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.DATAW (1 + LINE_SIZE + `CS_MEM_ADDR_WIDTH + `CS_LINE_WIDTH + MEM_TAG_WIDTH),
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.SIZE (MEM_REQ_BUF_ENABLE ? `OUT_REG_TO_EB_SIZE(MEM_OUT_REG) : 0),
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.OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG))
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) mem_req_buf (
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.clk (clk),
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.reset (mem_req_buf_reset),
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.valid_in (mem_req_valid_s),
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.ready_in (mem_req_ready_s),
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.data_in ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}),
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.data_out ({mem_bus_if.req_data.rw, mem_bus_if.req_data.byteen, mem_bus_if.req_data.addr, mem_bus_if.req_data.data, mem_bus_if.req_data.tag}),
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.valid_out (mem_bus_if.req_valid),
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.ready_out (mem_bus_if.req_ready)
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);
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///////////////////////////////////////////////////////////////////////////
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// Memory response buffering
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wire mem_rsp_valid_s;
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wire [`CS_LINE_WIDTH-1:0] mem_rsp_data_s;
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wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_s;
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wire mem_rsp_ready_s;
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`RESET_RELAY (mem_rsp_reset, reset);
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VX_elastic_buffer #(
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.DATAW (MEM_TAG_WIDTH + `CS_LINE_WIDTH),
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.SIZE (MRSQ_SIZE),
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.OUT_REG (MRSQ_SIZE > 2)
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) mem_rsp_queue (
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.clk (clk),
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.reset (mem_rsp_reset),
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.valid_in (mem_bus_if.rsp_valid),
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.ready_in (mem_bus_if.rsp_ready),
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.data_in ({mem_bus_if.rsp_data.tag, mem_bus_if.rsp_data.data}),
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.data_out ({mem_rsp_tag_s, mem_rsp_data_s}),
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.valid_out (mem_rsp_valid_s),
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.ready_out (mem_rsp_ready_s)
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);
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///////////////////////////////////////////////////////////////////////
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wire [`CS_LINE_SEL_BITS-1:0] init_line_sel;
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wire init_enable;
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`RESET_RELAY (init_reset, reset);
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VX_cache_init #(
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.CACHE_SIZE (CACHE_SIZE),
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.LINE_SIZE (LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.NUM_WAYS (NUM_WAYS)
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) cache_init (
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.clk (clk),
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.reset (init_reset),
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.addr_out (init_line_sel),
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.valid_out (init_enable)
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);
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///////////////////////////////////////////////////////////////////////
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wire [NUM_BANKS-1:0] per_bank_core_req_valid;
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wire [NUM_BANKS-1:0][`CS_LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr;
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wire [NUM_BANKS-1:0] per_bank_core_req_rw;
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wire [NUM_BANKS-1:0][WORD_SEL_WIDTH-1:0] per_bank_core_req_wsel;
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wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen;
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wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0] per_bank_core_req_data;
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wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_core_req_tag;
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wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_core_req_idx;
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wire [NUM_BANKS-1:0] per_bank_core_req_ready;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
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wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0] per_bank_core_rsp_data;
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wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_core_rsp_tag;
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wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_core_rsp_idx;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_ready;
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wire [NUM_BANKS-1:0] per_bank_mem_req_valid;
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wire [NUM_BANKS-1:0][`CS_MEM_ADDR_WIDTH-1:0] per_bank_mem_req_addr;
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wire [NUM_BANKS-1:0] per_bank_mem_req_rw;
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wire [NUM_BANKS-1:0][WORD_SEL_WIDTH-1:0] per_bank_mem_req_wsel;
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wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_mem_req_byteen;
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wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0] per_bank_mem_req_data;
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wire [NUM_BANKS-1:0][MSHR_ADDR_WIDTH-1:0] per_bank_mem_req_id;
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wire [NUM_BANKS-1:0] per_bank_mem_req_ready;
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wire [NUM_BANKS-1:0] per_bank_mem_rsp_ready;
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if (NUM_BANKS == 1) begin
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assign mem_rsp_ready_s = per_bank_mem_rsp_ready;
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end else begin
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assign mem_rsp_ready_s = per_bank_mem_rsp_ready[`CS_MEM_TAG_TO_BANK_ID(mem_rsp_tag_s)];
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end
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// Bank requests dispatch
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wire [NUM_REQS-1:0][CORE_REQ_DATAW-1:0] core_req_data_in;
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wire [NUM_BANKS-1:0][CORE_REQ_DATAW-1:0] core_req_data_out;
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wire [NUM_REQS-1:0][LINE_ADDR_WIDTH-1:0] core_req_line_addr;
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wire [NUM_REQS-1:0][BANK_SEL_WIDTH-1:0] core_req_bid;
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wire [NUM_REQS-1:0][WORD_SEL_WIDTH-1:0] core_req_wsel;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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if (WORDS_PER_LINE > 1) begin
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assign core_req_wsel[i] = core_req_addr[i][0 +: WORD_SEL_BITS];
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end else begin
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assign core_req_wsel[i] = '0;
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end
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assign core_req_line_addr[i] = core_req_addr[i][(BANK_SEL_BITS + WORD_SEL_BITS) +: LINE_ADDR_WIDTH];
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end
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if (NUM_BANKS > 1) begin
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_req_bid[i] = core_req_addr[i][WORD_SEL_BITS +: BANK_SEL_BITS];
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end
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end else begin
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assign core_req_bid = '0;
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end
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_req_data_in[i] = {
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core_req_line_addr[i],
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core_req_rw[i],
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core_req_wsel[i],
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core_req_byteen[i],
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core_req_data[i],
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core_req_tag[i]};
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end
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`ifdef PERF_ENABLE
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wire [`PERF_CTR_BITS-1:0] perf_collisions;
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`endif
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`RESET_RELAY (req_xbar_reset, reset);
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VX_stream_xbar #(
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.NUM_INPUTS (NUM_REQS),
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.NUM_OUTPUTS (NUM_BANKS),
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.DATAW (CORE_REQ_DATAW),
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.PERF_CTR_BITS (`PERF_CTR_BITS)
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) req_xbar (
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.clk (clk),
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.reset (req_xbar_reset),
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`ifdef PERF_ENABLE
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.collisions(perf_collisions),
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`else
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`UNUSED_PIN(collisions),
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`endif
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.valid_in (core_req_valid),
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.data_in (core_req_data_in),
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.sel_in (core_req_bid),
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.ready_in (core_req_ready),
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.valid_out (per_bank_core_req_valid),
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.data_out (core_req_data_out),
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.sel_out (per_bank_core_req_idx),
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.ready_out (per_bank_core_req_ready)
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);
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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assign {
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per_bank_core_req_addr[i],
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per_bank_core_req_rw[i],
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per_bank_core_req_wsel[i],
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per_bank_core_req_byteen[i],
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per_bank_core_req_data[i],
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per_bank_core_req_tag[i]} = core_req_data_out[i];
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end
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// Banks access
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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wire [`CS_LINE_ADDR_WIDTH-1:0] curr_bank_mem_req_addr;
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wire curr_bank_mem_rsp_valid;
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if (NUM_BANKS == 1) begin
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assign curr_bank_mem_rsp_valid = mem_rsp_valid_s;
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end else begin
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assign curr_bank_mem_rsp_valid = mem_rsp_valid_s && (`CS_MEM_TAG_TO_BANK_ID(mem_rsp_tag_s) == i);
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end
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`RESET_RELAY (bank_reset, reset);
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VX_cache_bank #(
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.BANK_ID (i),
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.INSTANCE_ID (INSTANCE_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.LINE_SIZE (LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.NUM_WAYS (NUM_WAYS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS),
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.CRSQ_SIZE (CRSQ_SIZE),
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.MSHR_SIZE (MSHR_SIZE),
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.MREQ_SIZE (MREQ_SIZE),
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.WRITE_ENABLE (WRITE_ENABLE),
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.UUID_WIDTH (UUID_WIDTH),
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.TAG_WIDTH (TAG_WIDTH),
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.CORE_OUT_REG (CORE_REQ_BUF_ENABLE ? 0 : CORE_OUT_REG),
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.MEM_OUT_REG (MEM_REQ_BUF_ENABLE ? 0 : MEM_OUT_REG)
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) bank (
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.clk (clk),
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.reset (bank_reset),
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`ifdef PERF_ENABLE
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.perf_read_misses (perf_read_miss_per_bank[i]),
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.perf_write_misses (perf_write_miss_per_bank[i]),
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.perf_mshr_stalls (perf_mshr_stall_per_bank[i]),
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`endif
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// Core request
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.core_req_valid (per_bank_core_req_valid[i]),
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.core_req_addr (per_bank_core_req_addr[i]),
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.core_req_rw (per_bank_core_req_rw[i]),
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.core_req_wsel (per_bank_core_req_wsel[i]),
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.core_req_byteen (per_bank_core_req_byteen[i]),
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.core_req_data (per_bank_core_req_data[i]),
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.core_req_tag (per_bank_core_req_tag[i]),
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.core_req_idx (per_bank_core_req_idx[i]),
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.core_req_ready (per_bank_core_req_ready[i]),
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// Core response
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.core_rsp_valid (per_bank_core_rsp_valid[i]),
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.core_rsp_data (per_bank_core_rsp_data[i]),
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.core_rsp_tag (per_bank_core_rsp_tag[i]),
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.core_rsp_idx (per_bank_core_rsp_idx[i]),
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.core_rsp_ready (per_bank_core_rsp_ready[i]),
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// Memory request
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.mem_req_valid (per_bank_mem_req_valid[i]),
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.mem_req_addr (curr_bank_mem_req_addr),
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.mem_req_rw (per_bank_mem_req_rw[i]),
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.mem_req_wsel (per_bank_mem_req_wsel[i]),
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.mem_req_byteen (per_bank_mem_req_byteen[i]),
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.mem_req_data (per_bank_mem_req_data[i]),
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.mem_req_id (per_bank_mem_req_id[i]),
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.mem_req_ready (per_bank_mem_req_ready[i]),
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// Memory response
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.mem_rsp_valid (curr_bank_mem_rsp_valid),
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.mem_rsp_data (mem_rsp_data_s),
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.mem_rsp_id (`CS_MEM_TAG_TO_REQ_ID(mem_rsp_tag_s)),
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.mem_rsp_ready (per_bank_mem_rsp_ready[i]),
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// initialization
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.init_enable (init_enable),
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.init_line_sel (init_line_sel)
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);
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if (NUM_BANKS == 1) begin
|
|
assign per_bank_mem_req_addr[i] = curr_bank_mem_req_addr;
|
|
end else begin
|
|
assign per_bank_mem_req_addr[i] = `CS_LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, i);
|
|
end
|
|
end
|
|
|
|
// Bank responses gather
|
|
|
|
wire [NUM_BANKS-1:0][CORE_RSP_DATAW-1:0] core_rsp_data_in;
|
|
wire [NUM_REQS-1:0][CORE_RSP_DATAW-1:0] core_rsp_data_out;
|
|
|
|
for (genvar i = 0; i < NUM_BANKS; ++i) begin
|
|
assign core_rsp_data_in[i] = {per_bank_core_rsp_data[i], per_bank_core_rsp_tag[i]};
|
|
end
|
|
|
|
`RESET_RELAY (rsp_xbar_reset, reset);
|
|
|
|
VX_stream_xbar #(
|
|
.NUM_INPUTS (NUM_BANKS),
|
|
.NUM_OUTPUTS (NUM_REQS),
|
|
.DATAW (CORE_RSP_DATAW)
|
|
) rsp_xbar (
|
|
.clk (clk),
|
|
.reset (rsp_xbar_reset),
|
|
`UNUSED_PIN (collisions),
|
|
.valid_in (per_bank_core_rsp_valid),
|
|
.data_in (core_rsp_data_in),
|
|
.sel_in (per_bank_core_rsp_idx),
|
|
.ready_in (per_bank_core_rsp_ready),
|
|
.valid_out (core_rsp_valid_s),
|
|
.data_out (core_rsp_data_out),
|
|
.ready_out (core_rsp_ready_s),
|
|
`UNUSED_PIN (sel_out)
|
|
);
|
|
|
|
for (genvar i = 0; i < NUM_REQS; ++i) begin
|
|
assign {core_rsp_data_s[i], core_rsp_tag_s[i]} = core_rsp_data_out[i];
|
|
end
|
|
|
|
///////////////////////////////////////////////////////////////////////////
|
|
|
|
wire mem_req_valid_p;
|
|
wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr_p;
|
|
wire mem_req_rw_p;
|
|
wire [WORD_SEL_WIDTH-1:0] mem_req_wsel_p;
|
|
wire [WORD_SIZE-1:0] mem_req_byteen_p;
|
|
wire [`CS_WORD_WIDTH-1:0] mem_req_data_p;
|
|
wire [MEM_TAG_WIDTH-1:0] mem_req_tag_p;
|
|
wire [MSHR_ADDR_WIDTH-1:0] mem_req_id_p;
|
|
wire mem_req_ready_p;
|
|
|
|
// Memory request arbitration
|
|
|
|
wire [NUM_BANKS-1:0][(`CS_MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + WORD_SIZE + WORD_SEL_WIDTH + `CS_WORD_WIDTH)-1:0] data_in;
|
|
|
|
for (genvar i = 0; i < NUM_BANKS; ++i) begin
|
|
assign data_in[i] = {per_bank_mem_req_addr[i],
|
|
per_bank_mem_req_rw[i],
|
|
per_bank_mem_req_wsel[i],
|
|
per_bank_mem_req_byteen[i],
|
|
per_bank_mem_req_data[i],
|
|
per_bank_mem_req_id[i]};
|
|
end
|
|
|
|
`RESET_RELAY (mem_req_arb_reset, reset);
|
|
|
|
VX_stream_arb #(
|
|
.NUM_INPUTS (NUM_BANKS),
|
|
.DATAW (`CS_MEM_ADDR_WIDTH + 1 + WORD_SEL_WIDTH + WORD_SIZE + `CS_WORD_WIDTH + MSHR_ADDR_WIDTH),
|
|
.ARBITER ("R")
|
|
) mem_req_arb (
|
|
.clk (clk),
|
|
.reset (mem_req_arb_reset),
|
|
.valid_in (per_bank_mem_req_valid),
|
|
.ready_in (per_bank_mem_req_ready),
|
|
.data_in (data_in),
|
|
.data_out ({mem_req_addr_p, mem_req_rw_p, mem_req_wsel_p, mem_req_byteen_p, mem_req_data_p, mem_req_id_p}),
|
|
.valid_out (mem_req_valid_p),
|
|
.ready_out (mem_req_ready_p),
|
|
`UNUSED_PIN (sel_out)
|
|
);
|
|
|
|
if (NUM_BANKS > 1) begin
|
|
wire [`CS_BANK_SEL_BITS-1:0] mem_req_bank_id = `CS_MEM_ADDR_TO_BANK_ID(mem_req_addr_p);
|
|
assign mem_req_tag_p = MEM_TAG_WIDTH'({mem_req_bank_id, mem_req_id_p});
|
|
end else begin
|
|
assign mem_req_tag_p = MEM_TAG_WIDTH'(mem_req_id_p);
|
|
end
|
|
|
|
// Memory request multi-port handling
|
|
|
|
assign mem_req_valid_s = mem_req_valid_p;
|
|
assign mem_req_addr_s = mem_req_addr_p;
|
|
assign mem_req_tag_s = mem_req_tag_p;
|
|
assign mem_req_ready_p = mem_req_ready_s;
|
|
|
|
if (WRITE_ENABLE != 0) begin
|
|
if (`CS_WORDS_PER_LINE > 1) begin
|
|
reg [LINE_SIZE-1:0] mem_req_byteen_r;
|
|
reg [`CS_LINE_WIDTH-1:0] mem_req_data_r;
|
|
|
|
always @(*) begin
|
|
mem_req_byteen_r = '0;
|
|
mem_req_data_r = 'x;
|
|
mem_req_byteen_r[mem_req_wsel_p * WORD_SIZE +: WORD_SIZE] = mem_req_byteen_p;
|
|
mem_req_data_r[mem_req_wsel_p * `CS_WORD_WIDTH +: `CS_WORD_WIDTH] = mem_req_data_p;
|
|
end
|
|
assign mem_req_rw_s = mem_req_rw_p;
|
|
assign mem_req_byteen_s = mem_req_byteen_r;
|
|
assign mem_req_data_s = mem_req_data_r;
|
|
end else begin
|
|
`UNUSED_VAR (mem_req_wsel_p)
|
|
assign mem_req_rw_s = mem_req_rw_p;
|
|
assign mem_req_byteen_s = mem_req_byteen_p;
|
|
assign mem_req_data_s = mem_req_data_p;
|
|
end
|
|
end else begin
|
|
`UNUSED_VAR (mem_req_byteen_p)
|
|
`UNUSED_VAR (mem_req_wsel_p)
|
|
`UNUSED_VAR (mem_req_data_p)
|
|
`UNUSED_VAR (mem_req_rw_p)
|
|
|
|
assign mem_req_rw_s = 0;
|
|
assign mem_req_byteen_s = {LINE_SIZE{1'b1}};
|
|
assign mem_req_data_s = '0;
|
|
end
|
|
|
|
`ifdef PERF_ENABLE
|
|
// per cycle: core_reads, core_writes
|
|
wire [`CLOG2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle;
|
|
wire [`CLOG2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle;
|
|
|
|
wire [NUM_REQS-1:0] perf_core_reads_per_req = core_req_valid & core_req_ready & ~core_req_rw;
|
|
wire [NUM_REQS-1:0] perf_core_writes_per_req = core_req_valid & core_req_ready & core_req_rw;
|
|
|
|
// per cycle: read misses, write misses, msrq stalls, pipeline stalls
|
|
wire [`CLOG2(NUM_BANKS+1)-1:0] perf_read_miss_per_cycle;
|
|
wire [`CLOG2(NUM_BANKS+1)-1:0] perf_write_miss_per_cycle;
|
|
wire [`CLOG2(NUM_BANKS+1)-1:0] perf_mshr_stall_per_cycle;
|
|
wire [`CLOG2(NUM_BANKS+1)-1:0] perf_crsp_stall_per_cycle;
|
|
|
|
`POP_COUNT(perf_core_reads_per_cycle, perf_core_reads_per_req);
|
|
`POP_COUNT(perf_core_writes_per_cycle, perf_core_writes_per_req);
|
|
`POP_COUNT(perf_read_miss_per_cycle, perf_read_miss_per_bank);
|
|
`POP_COUNT(perf_write_miss_per_cycle, perf_write_miss_per_bank);
|
|
`POP_COUNT(perf_mshr_stall_per_cycle, perf_mshr_stall_per_bank);
|
|
|
|
wire [NUM_REQS-1:0] perf_crsp_stall_per_req;
|
|
for (genvar i = 0; i < NUM_REQS; ++i) begin
|
|
assign perf_crsp_stall_per_req[i] = core_bus_if[i].rsp_valid && ~core_bus_if[i].rsp_ready;
|
|
end
|
|
|
|
`POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_req);
|
|
|
|
wire perf_mem_stall_per_cycle = mem_bus_if.req_valid && ~mem_bus_if.req_ready;
|
|
|
|
reg [`PERF_CTR_BITS-1:0] perf_core_reads;
|
|
reg [`PERF_CTR_BITS-1:0] perf_core_writes;
|
|
reg [`PERF_CTR_BITS-1:0] perf_read_misses;
|
|
reg [`PERF_CTR_BITS-1:0] perf_write_misses;
|
|
reg [`PERF_CTR_BITS-1:0] perf_mshr_stalls;
|
|
reg [`PERF_CTR_BITS-1:0] perf_mem_stalls;
|
|
reg [`PERF_CTR_BITS-1:0] perf_crsp_stalls;
|
|
|
|
always @(posedge clk) begin
|
|
if (reset) begin
|
|
perf_core_reads <= '0;
|
|
perf_core_writes <= '0;
|
|
perf_read_misses <= '0;
|
|
perf_write_misses <= '0;
|
|
perf_mshr_stalls <= '0;
|
|
perf_mem_stalls <= '0;
|
|
perf_crsp_stalls <= '0;
|
|
end else begin
|
|
perf_core_reads <= perf_core_reads + `PERF_CTR_BITS'(perf_core_reads_per_cycle);
|
|
perf_core_writes <= perf_core_writes + `PERF_CTR_BITS'(perf_core_writes_per_cycle);
|
|
perf_read_misses <= perf_read_misses + `PERF_CTR_BITS'(perf_read_miss_per_cycle);
|
|
perf_write_misses <= perf_write_misses + `PERF_CTR_BITS'(perf_write_miss_per_cycle);
|
|
perf_mshr_stalls <= perf_mshr_stalls + `PERF_CTR_BITS'(perf_mshr_stall_per_cycle);
|
|
perf_mem_stalls <= perf_mem_stalls + `PERF_CTR_BITS'(perf_mem_stall_per_cycle);
|
|
perf_crsp_stalls <= perf_crsp_stalls + `PERF_CTR_BITS'(perf_crsp_stall_per_cycle);
|
|
end
|
|
end
|
|
|
|
assign cache_perf.reads = perf_core_reads;
|
|
assign cache_perf.writes = perf_core_writes;
|
|
assign cache_perf.read_misses = perf_read_misses;
|
|
assign cache_perf.write_misses = perf_write_misses;
|
|
assign cache_perf.bank_stalls = perf_collisions;
|
|
assign cache_perf.mshr_stalls = perf_mshr_stalls;
|
|
assign cache_perf.mem_stalls = perf_mem_stalls;
|
|
assign cache_perf.crsp_stalls = perf_crsp_stalls;
|
|
`endif
|
|
|
|
endmodule
|