Blaise Tine 04249c3ee9 code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

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altera

updating fdiv/fsqrt bram hex files, reset_delay updaet

2021-02-04 09:02:18 -08:00

fpnew @ 1def7bb630

fpu implementation (part1)

2020-07-23 03:18:09 -07:00

VX_fp_class.sv

code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

VX_fp_cvt.sv

code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

VX_fp_div.sv

code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

VX_fp_fma.sv

code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

VX_fp_ncomp.sv

code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

VX_fp_rounding.sv

code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

VX_fp_sqrt.sv

code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

VX_fpu_define.vh

code refactoring for Vivado compatibility

2021-09-29 03:24:17 -04:00

VX_fpu_dpi.sv

code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

VX_fpu_fpga.sv

code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

VX_fpu_fpnew.sv

code refactoring for Vivado compatibility

2021-09-29 04:48:53 -04:00

VX_fpu_types.vh

code refactoring for Vivado compatibility

2021-09-29 03:24:17 -04:00