57 lines
1.7 KiB
Verilog
57 lines
1.7 KiB
Verilog
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`include "VX_define.v"
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module VX_scheduler (
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input wire clk,
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input wire reset,
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input wire memory_delay,
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input wire gpr_stage_delay,
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VX_frE_to_bckE_req_inter VX_bckE_req,
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VX_wb_inter VX_writeback_inter,
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output wire schedule_delay
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);
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reg rename_table[31:0];
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wire valid_wb = (VX_writeback_inter.wb != 0) && (|VX_writeback_inter.wb_valid) && (VX_writeback_inter.rd != 0);
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wire wb_inc = (VX_bckE_req.wb != 0) && (VX_bckE_req.rd != 0);
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// wire pass_through = ((VX_bckE_req.rs1 == VX_writeback_inter.rd) || (VX_bckE_req.rs2 == VX_writeback_inter.rd)) && valid_wb;
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// wire pass_through = 0;
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wire rs1_rename = rename_table[VX_bckE_req.rs1];
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wire rs2_rename = rename_table[VX_bckE_req.rs2];
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wire is_store = (VX_bckE_req.mem_write != `NO_MEM_WRITE);
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wire is_load = (VX_bckE_req.mem_read != `NO_MEM_READ);
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wire is_mem = is_store || is_load;
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wire rs1_rename_qual = (rs1_rename && (VX_bckE_req.rs1 != 0));
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wire rs2_rename_qual = (rs2_rename && (VX_bckE_req.rs2 != 0) && ((VX_bckE_req.rs2_src == `RS2_REG) || is_store)) || (VX_bckE_req.is_barrier) || (VX_bckE_req.is_wspawn);
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wire rename_valid = rs1_rename_qual || rs2_rename_qual ;
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assign schedule_delay = (rename_valid) && (|VX_bckE_req.valid) || (memory_delay && (is_mem)) || (gpr_stage_delay && is_mem);
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integer i;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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for (i = 0; i < 32; i = i + 1) rename_table[i] <= 0;
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end else begin
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if (valid_wb ) rename_table[VX_writeback_inter.rd] <= 0;
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if (!schedule_delay && wb_inc) rename_table[VX_bckE_req.rd] <= 1;
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end
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end
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endmodule |