213 lines
7.8 KiB
Verilog
213 lines
7.8 KiB
Verilog
`include "VX_define.vh"
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module VX_alu_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_alu_req_if alu_req_if,
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// Outputs
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VX_branch_ctl_if branch_ctl_if,
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VX_commit_if alu_commit_if
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);
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`UNUSED_PARAM (CORE_ID)
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reg [`NUM_THREADS-1:0][31:0] alu_result;
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wire [`NUM_THREADS-1:0][31:0] add_result;
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wire [`NUM_THREADS-1:0][32:0] sub_result;
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wire [`NUM_THREADS-1:0][31:0] shr_result;
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reg [`NUM_THREADS-1:0][31:0] msc_result;
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wire stall_in, stall_out;
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`UNUSED_VAR (alu_req_if.op_mod)
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wire is_br_op = `ALU_IS_BR(alu_req_if.op_mod);
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wire [`ALU_BITS-1:0] alu_op = `ALU_OP(alu_req_if.op_type);
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wire [`BR_BITS-1:0] br_op = `BR_OP(alu_req_if.op_type);
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wire alu_signed = `ALU_SIGNED(alu_op);
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wire [1:0] alu_op_class = `ALU_OP_CLASS(alu_op);
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wire is_sub = (alu_op == `ALU_SUB);
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wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in1_PC = alu_req_if.use_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1;
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wire [`NUM_THREADS-1:0][31:0] alu_in2_imm = alu_req_if.use_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
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wire [`NUM_THREADS-1:0][31:0] alu_in2_less = (alu_req_if.use_imm && ~is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign add_result[i] = alu_in1_PC[i] + alu_in2_imm[i];
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [32:0] sub_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]};
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wire [32:0] sub_in2 = {alu_signed & alu_in2_less[i][31], alu_in2_less[i]};
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assign sub_result[i] = sub_in1 - sub_in2;
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [32:0] shr_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]};
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assign shr_result[i] = 32'($signed(shr_in1) >>> alu_in2_imm[i][4:0]);
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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always @(*) begin
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case (alu_op)
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`ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i];
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`ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i];
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`ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i];
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//`ALU_SLL,
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default: msc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0];
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endcase
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end
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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always @(*) begin
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case (alu_op_class)
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2'b00: alu_result[i] = add_result[i]; // ADD, LUI, AUIPC
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2'b01: alu_result[i] = {31'b0, sub_result[i][32]}; // SLTU, SLT
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2'b10: alu_result[i] = is_sub ? sub_result[i][31:0] // SUB
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: shr_result[i]; // SRL, SRA
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// 2'b11,
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default: alu_result[i] = msc_result[i]; // AND, OR, XOR, SLL
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endcase
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end
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end
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// branch
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wire is_jal = is_br_op && (br_op == `BR_JAL || br_op == `BR_JALR);
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wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : alu_result;
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wire [31:0] br_dest = add_result[alu_req_if.tid];
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wire [32:0] cmp_result = sub_result[alu_req_if.tid];
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wire is_less = cmp_result[32];
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wire is_equal = ~(| cmp_result[31:0]);
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wire br_neg = `BR_NEG(br_op);
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wire br_less = `BR_LESS(br_op);
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wire br_static = `BR_STATIC(br_op);
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wire br_taken = ((br_less ? is_less : is_equal) ^ br_neg) | br_static;
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// output
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wire result_valid;
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wire [`NW_BITS-1:0] result_wid;
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wire [`NUM_THREADS-1:0] result_tmask;
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wire [31:0] result_PC;
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wire [`NR_BITS-1:0] result_rd;
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wire result_wb;
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wire [`NUM_THREADS-1:0][31:0] result_data;
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wire result_is_br;
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`ifdef EXT_M_ENABLE
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wire mul_ready_in;
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wire mul_valid_out;
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wire mul_ready_out;
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wire [`NW_BITS-1:0] mul_wid;
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wire [`NUM_THREADS-1:0] mul_tmask;
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wire [31:0] mul_PC;
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wire [`NR_BITS-1:0] mul_rd;
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wire mul_wb;
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wire [`NUM_THREADS-1:0][31:0] mul_data;
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wire is_mul_op = `ALU_IS_MUL(alu_req_if.op_mod);
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VX_muldiv muldiv (
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.clk (clk),
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.reset (reset),
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// Inputs
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.alu_op (`MUL_OP(alu_req_if.op_type)),
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.wid_in (alu_req_if.wid),
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.tmask_in (alu_req_if.tmask),
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.PC_in (alu_req_if.PC),
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.rd_in (alu_req_if.rd),
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.wb_in (alu_req_if.wb),
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.alu_in1 (alu_req_if.rs1_data),
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.alu_in2 (alu_req_if.rs2_data),
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// Outputs
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.wid_out (mul_wid),
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.tmask_out (mul_tmask),
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.PC_out (mul_PC),
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.rd_out (mul_rd),
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.wb_out (mul_wb),
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.data_out (mul_data),
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// handshake
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.valid_in (alu_req_if.valid && is_mul_op),
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.ready_in (mul_ready_in),
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.valid_out (mul_valid_out),
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.ready_out (mul_ready_out)
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);
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assign stall_in = (is_mul_op && ~mul_ready_in)
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|| (~is_mul_op && (mul_valid_out || stall_out));
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assign mul_ready_out = ~stall_out;
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assign result_valid = mul_valid_out || (alu_req_if.valid && ~is_mul_op);
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assign result_wid = mul_valid_out ? mul_wid : alu_req_if.wid;
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assign result_tmask = mul_valid_out ? mul_tmask : alu_req_if.tmask;
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assign result_PC = mul_valid_out ? mul_PC : alu_req_if.PC;
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assign result_rd = mul_valid_out ? mul_rd : alu_req_if.rd;
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assign result_wb = mul_valid_out ? mul_wb : alu_req_if.wb;
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assign result_data = mul_valid_out ? mul_data : alu_jal_result;
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assign result_is_br = ~mul_valid_out && is_br_op;
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`else
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assign stall_in = stall_out;
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assign result_valid = alu_req_if.valid;
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assign result_wid = alu_req_if.wid;
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assign result_tmask = alu_req_if.tmask;
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assign result_PC = alu_req_if.PC;
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assign result_rd = alu_req_if.rd;
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assign result_wb = alu_req_if.wb;
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assign result_data = alu_jal_result;
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assign result_is_br = is_br_op;
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`endif
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wire is_br_op_r;
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assign stall_out = ~alu_commit_if.ready && alu_commit_if.valid;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + 1 + 32),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall_out),
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.data_in ({result_valid, result_wid, result_tmask, result_PC, result_rd, result_wb, result_data, result_is_br, br_taken, br_dest}),
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.data_out ({alu_commit_if.valid, alu_commit_if.wid, alu_commit_if.tmask, alu_commit_if.PC, alu_commit_if.rd, alu_commit_if.wb, alu_commit_if.data, is_br_op_r, branch_ctl_if.taken, branch_ctl_if.dest})
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);
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assign alu_commit_if.eop = 1'b1;
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assign branch_ctl_if.valid = alu_commit_if.valid && alu_commit_if.ready && is_br_op_r;
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assign branch_ctl_if.wid = alu_commit_if.wid;
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// can accept new request?
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assign alu_req_if.ready = ~stall_in;
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (branch_ctl_if.valid) begin
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$display("%t: core%0d-branch: wid=%0d, PC=%0h, taken=%b, dest=%0h", $time, CORE_ID,
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branch_ctl_if.wid, alu_commit_if.PC, branch_ctl_if.taken, branch_ctl_if.dest);
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end
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end
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`endif
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endmodule |