49 lines
864 B
Verilog
49 lines
864 B
Verilog
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module VX_generic_queue
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#(
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parameter DATAW = 4,
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parameter SIZE = 277
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)
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(
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input wire clk,
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input wire reset,
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input wire push,
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input wire[DATAW-1:0] in_data,
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input wire pop,
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output wire[DATAW-1:0] out_data,
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output wire empty,
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output wire full
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);
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reg[DATAW-1:0] data[SIZE-1:0];
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reg[$clog2(SIZE)-1:0] head;
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reg[$clog2(SIZE)-1:0] tail;
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assign empty = head == tail;
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assign full = head == (tail+1);
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integer i;
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always @(posedge clk) begin
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if (reset) begin
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head <= 0;
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tail <= 0;
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for (i = 0; i < SIZE; i=i+1) begin
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data[i] <= 0;
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end
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end else begin
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if (push && !full) begin
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data[tail] <= in_data;
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tail <= tail+1;
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end
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if (pop && !empty) begin
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head <= head + 1;
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end
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end
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end
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assign out_data = data[head];
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endmodule |