26 lines
600 B
Verilog
26 lines
600 B
Verilog
`include "VX_platform.vh"
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module VX_priority_encoder #(
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parameter DATAW = 1,
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parameter LDATAW = `LOG2UP(DATAW)
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) (
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input wire [DATAW-1:0] data_in,
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output wire [LDATAW-1:0] data_out,
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output wire valid_out
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);
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reg [LDATAW-1:0] data_out_r;
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always @(*) begin
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data_out_r = 'x;
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for (integer i = 0; i < DATAW; i++) begin
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if (data_in[i]) begin
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data_out_r = LDATAW'(i);
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break;
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end
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end
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end
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assign data_out = data_out_r;
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assign valid_out = (| data_in);
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endmodule |