112 lines
2.7 KiB
Verilog
112 lines
2.7 KiB
Verilog
`include "VX_define.vh"
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module VX_front_end (
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input wire clk,
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input wire reset,
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input wire schedule_delay,
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VX_warp_ctl_if warp_ctl_if,
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VX_gpu_dcache_rsp_if icache_rsp_if,
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VX_gpu_dcache_req_if icache_req_if,
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VX_jal_rsp_if jal_rsp_if,
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VX_branch_rsp_if branch_rsp_if,
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VX_frE_to_bckE_req_if bckE_req_if,
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output wire fetch_ebreak
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);
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VX_inst_meta_if fe_inst_meta_fi();
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VX_inst_meta_if fe_inst_meta_fi2();
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VX_inst_meta_if fe_inst_meta_id();
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VX_frE_to_bckE_req_if frE_to_bckE_req_if();
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VX_inst_meta_if fd_inst_meta_de();
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wire total_freeze = schedule_delay;
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wire icache_stage_delay;
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wire vortex_ebreak;
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wire terminate_sim;
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wire[`NW_BITS-1:0] icache_stage_wid;
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wire[`NUM_THREADS-1:0] icache_stage_valids;
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assign fetch_ebreak = vortex_ebreak || terminate_sim;
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VX_wstall_if wstall_if();
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VX_join_if join_if();
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VX_fetch fetch(
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.clk (clk),
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.reset (reset),
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.icache_stage_wid (icache_stage_wid),
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.icache_stage_valids(icache_stage_valids),
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.wstall_if (wstall_if),
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.join_if (join_if),
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.schedule_delay (schedule_delay),
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.jal_rsp_if (jal_rsp_if),
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.warp_ctl_if (warp_ctl_if),
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.icache_stage_delay (icache_stage_delay),
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.branch_rsp_if (branch_rsp_if),
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.ebreak (vortex_ebreak), // fetch_ebreak
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.fe_inst_meta_fi (fe_inst_meta_fi)
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);
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wire freeze_fi_reg = total_freeze || icache_stage_delay;
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VX_f_d_reg f_i_reg(
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.clk (clk),
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.reset (reset),
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.freeze (freeze_fi_reg),
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.fe_inst_meta_fd(fe_inst_meta_fi),
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.fd_inst_meta_de(fe_inst_meta_fi2)
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);
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VX_icache_stage icache_stage(
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.clk (clk),
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.reset (reset),
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.total_freeze (total_freeze),
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.icache_stage_delay (icache_stage_delay),
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.icache_stage_valids(icache_stage_valids),
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.icache_stage_wid (icache_stage_wid),
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.fe_inst_meta_fi (fe_inst_meta_fi2),
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.fe_inst_meta_id (fe_inst_meta_id),
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.icache_rsp_if (icache_rsp_if),
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.icache_req_if (icache_req_if)
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);
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VX_i_d_reg i_d_reg(
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.clk (clk),
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.reset (reset),
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.freeze (total_freeze),
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.fe_inst_meta_fd (fe_inst_meta_id),
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.fd_inst_meta_de (fd_inst_meta_de)
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);
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VX_decode decode(
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.fd_inst_meta_de (fd_inst_meta_de),
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.frE_to_bckE_req_if (frE_to_bckE_req_if),
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.wstall_if (wstall_if),
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.join_if (join_if),
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.terminate_sim (terminate_sim)
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);
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wire no_br_stall = 0;
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VX_d_e_reg d_e_reg(
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.clk (clk),
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.reset (reset),
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.branch_stall (no_br_stall),
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.freeze (total_freeze),
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.frE_to_bckE_req_if (frE_to_bckE_req_if),
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.bckE_req_if (bckE_req_if)
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);
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endmodule
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