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vortex/hw/rtl/interfaces
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Blaise Tine ac1883a13f tabs cleanup
2020-11-28 17:08:01 -05:00
..
VX_alu_req_if.v
SCOPE update
2020-09-05 10:52:59 -07:00
VX_branch_ctl_if.v
pipeline refactoring - fmax >= 222 mhz
2020-08-14 21:50:14 -07:00
VX_cache_core_req_if.v
mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
2020-09-19 14:45:42 -04:00
VX_cache_core_rsp_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_cache_dram_req_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_cache_dram_rsp_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_cache_snp_req_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_cache_snp_rsp_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_cmt_to_csr_if.v
fixed FPU-CSR data dependence
2020-11-25 09:05:38 -08:00
VX_commit_if.v
fixed FPU-CSR data dependence
2020-11-25 09:05:38 -08:00
VX_csr_io_req_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_csr_io_rsp_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_csr_req_if.v
SCOPE update
2020-09-05 10:52:59 -07:00
VX_decode_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_fpu_req_if.v
pipeline optimization: fixed GPR fanout delay to execute units
2020-11-07 02:01:21 -08:00
VX_fpu_to_cmt_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_fpu_to_csr_if.v
tabs cleanup
2020-11-28 17:08:01 -05:00
VX_gpr_req_if.v
SCOPE update
2020-09-05 10:52:59 -07:00
VX_gpr_rsp_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_gpu_req_if.v
SCOPE update
2020-09-05 10:52:59 -07:00
VX_ifetch_req_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_ifetch_rsp_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_join_if.v
optimize warp_sched
2020-08-24 05:36:00 -07:00
VX_lsu_req_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_mul_req_if.v
SCOPE update
2020-09-05 10:52:59 -07:00
VX_warp_ctl_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_writeback_if.v
tabs cleanup
2020-11-28 17:08:01 -05:00
VX_wstall_if.v
tabs cleanup
2020-11-28 17:08:01 -05:00