22 lines
307 B
Verilog
22 lines
307 B
Verilog
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module VX_rename (
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input wire clk,
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input wire[`NW_M1:0] warp_num,
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input wire[4:0] rs1,
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input wire[4:0] rs2,
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input wire[4:0] rd,
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output wire stall,
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);
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reg[31:0] rename[`NW-1:0];
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assign stall = rename[warp_num][rs1] || rename[warp_num][rs2];
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alwa
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endmodule |