15 lines
291 B
Verilog
15 lines
291 B
Verilog
module VX_lsu_addr_gen (
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input wire[`NT_M1:0][31:0] base_address,
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input wire[31:0] offset,
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output wire[`NT_M1:0][31:0] address
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);
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genvar index;
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for (index = 0; index < `NT; index = index + 1)
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begin
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assign address[index] = base_address[index] + offset;
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end
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endmodule |