c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
80 lines
2.4 KiB
Systemverilog
80 lines
2.4 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_gbar_arb #(
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parameter NUM_REQS = 1,
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parameter OUT_REG = 0,
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parameter `STRING ARBITER = "R"
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) (
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input wire clk,
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input wire reset,
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VX_gbar_bus_if.slave bus_in_if [NUM_REQS],
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VX_gbar_bus_if.master bus_out_if
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);
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localparam REQ_DATAW = `NB_WIDTH + `NC_WIDTH + `NC_WIDTH;
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// arbitrate request
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wire [NUM_REQS-1:0] req_valid_in;
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wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_in;
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wire [NUM_REQS-1:0] req_ready_in;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign req_valid_in[i] = bus_in_if[i].req_valid;
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assign req_data_in[i] = {bus_in_if[i].req_id, bus_in_if[i].req_size_m1, bus_in_if[i].req_core_id};
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assign bus_in_if[i].req_ready = req_ready_in[i];
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end
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VX_stream_arb #(
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.NUM_INPUTS (NUM_REQS),
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.NUM_OUTPUTS (1),
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.DATAW (REQ_DATAW),
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.ARBITER (ARBITER),
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.OUT_REG (OUT_REG)
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) req_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (req_valid_in),
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.ready_in (req_ready_in),
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.data_in (req_data_in),
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.data_out ({bus_out_if.req_id, bus_out_if.req_size_m1, bus_out_if.req_core_id}),
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.valid_out (bus_out_if.req_valid),
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.ready_out (bus_out_if.req_ready),
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`UNUSED_PIN (sel_out)
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);
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// broadcast response
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reg rsp_valid;
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reg [`NB_WIDTH-1:0] rsp_id;
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always @(posedge clk) begin
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if (reset) begin
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rsp_valid <= 0;
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end else begin
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rsp_valid <= bus_out_if.rsp_valid;
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end
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rsp_id <= bus_out_if.rsp_id;
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end
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign bus_in_if[i].rsp_valid = rsp_valid;
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assign bus_in_if[i].rsp_id = rsp_id;
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end
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endmodule
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