125 lines
3.6 KiB
Verilog
125 lines
3.6 KiB
Verilog
`include "VX_platform.vh"
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module VX_stream_arbiter #(
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parameter NUM_REQS = 1,
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parameter DATAW = 1,
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parameter TYPE = "R",
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parameter LOCK_ENABLE = 1,
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parameter BUFFERED = 0
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) (
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input wire clk,
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input wire reset,
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input wire [NUM_REQS-1:0] valid_in,
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input wire [NUM_REQS-1:0][DATAW-1:0] data_in,
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output wire [NUM_REQS-1:0] ready_in,
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output wire valid_out,
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output wire [DATAW-1:0] data_out,
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input wire ready_out
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);
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localparam LOG_NUM_REQS = $clog2(NUM_REQS);
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if (NUM_REQS > 1) begin
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wire sel_valid;
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wire sel_ready;
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wire [NUM_REQS-1:0] sel_1hot;
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if (TYPE == "X") begin
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VX_fixed_arbiter #(
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.NUM_REQS(NUM_REQS),
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.LOCK_ENABLE(LOCK_ENABLE)
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) sel_arb (
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.clk (clk),
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.reset (reset),
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.requests (valid_in),
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.enable (sel_ready),
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.grant_valid (sel_valid),
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.grant_onehot (sel_1hot),
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`UNUSED_PIN (grant_index)
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);
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end else if (TYPE == "R") begin
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VX_rr_arbiter #(
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.NUM_REQS(NUM_REQS),
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.LOCK_ENABLE(LOCK_ENABLE)
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) sel_arb (
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.clk (clk),
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.reset (reset),
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.requests (valid_in),
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.enable (sel_ready),
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.grant_valid (sel_valid),
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.grant_onehot (sel_1hot),
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`UNUSED_PIN (grant_index)
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);
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end else if (TYPE == "F") begin
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VX_fair_arbiter #(
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.NUM_REQS(NUM_REQS),
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.LOCK_ENABLE(LOCK_ENABLE)
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) sel_arb (
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.clk (clk),
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.reset (reset),
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.requests (valid_in),
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.enable (sel_ready),
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.grant_valid (sel_valid),
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.grant_onehot (sel_1hot),
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`UNUSED_PIN (grant_index)
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);
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end else if (TYPE == "M") begin
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VX_matrix_arbiter #(
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.NUM_REQS(NUM_REQS),
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.LOCK_ENABLE(LOCK_ENABLE)
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) sel_arb (
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.clk (clk),
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.reset (reset),
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.requests (valid_in),
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.enable (sel_ready),
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.grant_valid (sel_valid),
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.grant_onehot (sel_1hot),
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`UNUSED_PIN (grant_index)
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);
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end else begin
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$error ("invalid parameter");
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end
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wire [DATAW-1:0] data_in_sel;
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VX_onehot_mux #(
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.DATAW (DATAW),
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.N (NUM_REQS)
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) data_in_mux (
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.data_in (data_in),
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.sel_in (sel_1hot),
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.data_out (data_in_sel)
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);
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VX_skid_buffer #(
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.DATAW (DATAW),
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.PASSTHRU (!BUFFERED)
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) out_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (sel_valid),
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.data_in (data_in_sel),
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.ready_in (sel_ready),
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.valid_out (valid_out),
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.data_out (data_out),
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.ready_out (ready_out)
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);
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign ready_in[i] = sel_1hot[i] && sel_ready;
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end
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign valid_out = valid_in;
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assign data_out = data_in;
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assign ready_in = ready_out;
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end
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endmodule |