188 lines
5.8 KiB
Verilog
188 lines
5.8 KiB
Verilog
`include "VX_platform.vh"
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module VX_generic_queue #(
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parameter DATAW = 1,
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parameter SIZE = 2,
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parameter BUFFERED = 0,
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parameter ADDRW = $clog2(SIZE),
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parameter SIZEW = $clog2(SIZE+1),
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parameter FASTRAM = 1
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) (
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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output wire empty,
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output wire full,
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output wire [SIZEW-1:0] size
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);
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`STATIC_ASSERT(`ISPOW2(SIZE), ("must be 0 or power of 2!"))
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if (SIZE == 1) begin
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reg [DATAW-1:0] head_r;
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reg size_r;
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always @(posedge clk) begin
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if (reset) begin
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head_r <= 0;
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size_r <= 0;
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end else begin
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if (push && !pop) begin
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assert(!full);
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size_r <= 1;
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end else if (pop && !push) begin
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assert(!empty);
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size_r <= 0;
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end
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if (push) begin
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head_r <= data_in;
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end
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end
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end
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assign data_out = head_r;
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assign empty = (size_r == 0);
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assign full = (size_r != 0);
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assign size = size_r;
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end else begin
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reg empty_r;
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reg full_r;
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reg [ADDRW-1:0] used_r;
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always @(posedge clk) begin
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if (reset) begin
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empty_r <= 1;
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full_r <= 0;
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used_r <= 0;
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end else begin
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if (push) begin
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assert(!full);
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if (!pop) begin
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empty_r <= 0;
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if (used_r == ADDRW'(SIZE-1)) begin
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full_r <= 1;
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end
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used_r <= used_r + ADDRW'(1);
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end
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end
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if (pop) begin
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assert(!empty);
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if (!push) begin
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full_r <= 0;
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if (used_r == ADDRW'(1)) begin
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empty_r <= 1;
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end;
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used_r <= used_r - ADDRW'(1);
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end
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end
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end
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end
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if (0 == BUFFERED) begin
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reg [ADDRW:0] rd_ptr_r;
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reg [ADDRW:0] wr_ptr_r;
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wire [ADDRW-1:0] rd_ptr_a = rd_ptr_r[ADDRW-1:0];
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wire [ADDRW-1:0] wr_ptr_a = wr_ptr_r[ADDRW-1:0];
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr_r <= 0;
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wr_ptr_r <= 0;
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end else begin
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if (push) begin
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wr_ptr_r <= wr_ptr_r + (ADDRW+1)'(1);
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end
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if (pop) begin
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rd_ptr_r <= rd_ptr_r + (ADDRW+1)'(1);
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end
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end
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end
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VX_dp_ram #(
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.DATAW(DATAW),
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.SIZE(SIZE),
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.BUFFERED(0),
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.RWCHECK(1),
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.FASTRAM(FASTRAM)
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) dp_ram (
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.clk(clk),
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.waddr(wr_ptr_a),
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.raddr(rd_ptr_a),
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.wren(push),
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.byteen(1'b1),
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.rden(pop),
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.din(data_in),
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.dout(data_out)
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);
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end else begin
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wire [DATAW-1:0] dout;
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reg [DATAW-1:0] din_r;
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reg [ADDRW-1:0] wr_ptr_r;
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reg [ADDRW-1:0] rd_ptr_r;
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reg [ADDRW-1:0] rd_ptr_n_r;
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reg bypass_r;
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always @(posedge clk) begin
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if (reset) begin
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wr_ptr_r <= 0;
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rd_ptr_r <= 0;
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rd_ptr_n_r <= 1;
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end else begin
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if (push) begin
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wr_ptr_r <= wr_ptr_r + ADDRW'(1);
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end
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if (pop) begin
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rd_ptr_r <= rd_ptr_n_r;
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if (SIZE > 2) begin
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rd_ptr_n_r <= rd_ptr_r + ADDRW'(2);
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end else begin // (SIZE == 2);
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rd_ptr_n_r <= ~rd_ptr_n_r;
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end
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end
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end
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end
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always @(posedge clk) begin
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if (push && (empty_r || ((used_r == ADDRW'(1)) && pop))) begin
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bypass_r <= 1;
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din_r <= data_in;
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end else if (pop)
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bypass_r <= 0;
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end
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VX_dp_ram #(
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.DATAW(DATAW),
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.SIZE(SIZE),
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.BUFFERED(1),
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.RWCHECK(0),
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.FASTRAM(FASTRAM)
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) dp_ram (
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.clk(clk),
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.waddr(wr_ptr_r),
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.raddr(rd_ptr_n_r),
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.wren(push),
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.byteen(1'b1),
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.rden(pop),
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.din(data_in),
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.dout(dout)
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);
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assign data_out = bypass_r ? din_r : dout;
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end
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assign empty = empty_r;
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assign full = full_r;
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assign size = {full_r, used_r};
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end
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endmodule
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