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ad9623b7ddd559dcbe53102ead54c8ca271dfd3e
vortex/models/memory/cln28hpc/rf2_32x128_wm1
History
Lingjun Zhu 50d567d70c Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
2019-10-28 14:49:55 -04:00
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vsim
Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
2019-10-28 14:49:55 -04:00
env_vsim
Created a testbench and simulated the read/write of the register file
2019-10-18 22:55:34 -04:00
Makefile
Updated makefile
2019-10-16 19:56:11 -04:00
rf2_32x128_wm1_antenna.clf
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_ff_0p99v_0p99v_m40c.avm
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_ff_0p99v_0p99v_m40c.dat
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib_sh5p1cm
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_ff_0p99v_0p99v_m40c.ps
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_rtl.v
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_ss_0p81v_0p81v_125c.avm
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_ss_0p81v_0p81v_125c.dat
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_ss_0p81v_0p81v_125c.lib
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_ss_0p81v_0p81v_125c.ps
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_tt_0p81v_0p81v_0c.avm
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_tt_0p81v_0p81v_0c.dat
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_tt_0p81v_0p81v_0c.lib
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1_tt_0p81v_0p81v_0c.ps
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1.bitmap
Move the memory models from Cache_Progress to Master branch
2019-10-13 13:13:42 -04:00
rf2_32x128_wm1.cpf
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1.ctl
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1.lef
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1.mdt
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1.memlib
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1.tv
Generate LIB files for rf2_32x128_wm1
2019-10-14 17:08:18 -04:00
rf2_32x128_wm1.v
Integrated Shared Memory
2019-10-22 05:03:47 -04:00
testbench.cpp
Still giving sc_time_stamp error
2019-10-16 19:45:21 -04:00