33 lines
392 B
Verilog
33 lines
392 B
Verilog
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`include "VX_define.v"
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`ifndef VX_JAL_RSP
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`define VX_JAL_RSP
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interface VX_jal_response_inter ();
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wire jal;
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wire[31:0] jal_dest;
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wire[`NW_M1:0] jal_warp_num;
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// source-side view
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modport snk (
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input jal,
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input jal_dest,
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input jal_warp_num
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);
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// source-side view
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modport src (
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output jal,
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output jal_dest,
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output jal_warp_num
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);
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endinterface
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`endif |