34 lines
701 B
Verilog
34 lines
701 B
Verilog
`include "VX_define.vh"
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`TRACING_OFF
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module VX_gpr_ram_i #(
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parameter DATAW = 1,
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parameter DEPTH = 1,
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parameter ADDRW = $clog2(DEPTH)
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) (
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input wire clk,
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input wire wren,
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input wire [ADDRW-1:0] waddr,
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input wire [DATAW-1:0] wdata,
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input wire [ADDRW-1:0] raddr1,
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input wire [ADDRW-1:0] raddr2,
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output wire [DATAW-1:0] rdata1,
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output wire [DATAW-1:0] rdata2
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);
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reg [DATAW-1:0] mem [DEPTH-1:0];
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initial mem = '{default: 0};
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always @(posedge clk) begin
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if (wren) begin
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mem [waddr] <= wdata;
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end
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end
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assign rdata1 = mem [raddr1];
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assign rdata2 = mem [raddr2];
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endmodule
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`TRACING_ON |