Blaise Tine abe32ed553 cache optimization - moved read requests to stage1 and eliminating stage3

2020-12-31 07:40:58 -08:00

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VX_bank.v

cache optimization - moved read requests to stage1 and eliminating stage3

2020-12-31 07:40:58 -08:00

VX_cache_config.vh

added support for write-through cache, removed cache snooping support

2020-12-23 23:51:02 -08:00

VX_cache_core_req_bank_sel.v

critical path optimization - fpga fmax @4c = ~212 mhz

2020-12-26 03:28:32 -08:00

VX_cache_core_rsp_merge.v

critical path optimization - fpga fmax @4c = ~212 mhz

2020-12-26 03:28:32 -08:00

VX_cache.v

cache optimization - moved read requests to stage1 and eliminating stage3

2020-12-31 07:40:58 -08:00

VX_data_access.v

cache optimization - moved read requests to stage1 and eliminating stage3

2020-12-31 07:40:58 -08:00

VX_data_store.v

cache optimization - moved read requests to stage1 and eliminating stage3

2020-12-31 07:40:58 -08:00

VX_miss_resrv.v

cache optimization - moved read requests to stage1 and eliminating stage3

2020-12-31 07:40:58 -08:00

VX_tag_access.v

cache optimization - moved read requests to stage1 and eliminating stage3

2020-12-31 07:40:58 -08:00

VX_tag_store.v

adding new performance counters (banks utilization and DRAM bus utilization)

2020-12-22 12:33:45 -08:00