123 lines
5.4 KiB
Verilog
123 lines
5.4 KiB
Verilog
`include "VX_platform.vh"
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`include "VX_define.vh"
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module VX_tex_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_tex_req_if tex_req_if,
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VX_tex_csr_if tex_csr_if,
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// Outputs
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VX_tex_rsp_if tex_rsp_if
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// VX_commit_if gpu_commit_if
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// // Texture Request
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// input wire tex_req_valid,
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// input wire [`TADDRW-1:0] tex_req_u,
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// input wire [`TADDRW-1:0] tex_req_v,
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// input wire [`MADDRW-1:0] tex_req_addr,
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// input wire [`MAXWTW-1:0] tex_req_width,
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// input wire [`MAXHTW-1:0] tex_req_height,
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// input wire [`MAXFTW-1:0] tex_req_format,
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// input wire [`MAXFMW-1:0] tex_req_filter,
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// input wire [`MAXAMW-1:0] tex_req_clamp,
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// input wire [`TAGW-1:0] tex_req_tag,
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// output wire tex_req_ready,
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// // Texture Response
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// output wire tex_rsp_valid,
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// output wire [`TAGW-1:0] tex_rsp_tag,
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// input wire [`DATAW-1:0] tex_rsp_data,
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// input wire tex_rsp_ready,
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// Cache Request
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// output wire [NUMCRQS-1:0] cache_req_valids,
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// output wire [NUMCRQS-1:0][MADDRW-1:0] cache_req_addrs,
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// input wire cache_req_ready,
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// Cache Response
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// input wire cache_rsp_valid,
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// input wire [MADDRW-1:0] cache_rsp_addr,
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// input wire [DATAW-1:0] cache_rsp_data,
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// output wire cache_rsp_ready
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);
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// `UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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`UNUSED_VAR (reset)
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`UNUSED_VAR(tex_addr)
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`UNUSED_VAR(tex_format)
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`UNUSED_VAR(tex_width)
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`UNUSED_VAR(tex_height)
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`UNUSED_VAR(tex_stride)
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`UNUSED_VAR(tex_wrap_u)
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`UNUSED_VAR(tex_wrap_v)
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`UNUSED_VAR(tex_min_filter)
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`UNUSED_VAR(tex_max_filter)
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reg [`CSR_WIDTH-1:0] tex_addr [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_format [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_width [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_height [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_stride [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_wrap_u [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_wrap_v [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_min_filter [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_max_filter [`NUM_TEX_UNITS-1: 0];
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//tex csr programming, need to make make consistent with `NUM_TEX_UNITS
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always @(posedge clk ) begin
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if (tex_csr_if.write_enable) begin
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case (tex_csr_if.write_addr)
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`CSR_TEX0_ADDR : tex_addr[0] <= tex_csr_if.write_data;
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`CSR_TEX0_FORMAT : tex_format[0] <= tex_csr_if.write_data;
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`CSR_TEX0_WIDTH : tex_width[0] <= tex_csr_if.write_data;
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`CSR_TEX0_HEIGHT : tex_height[0] <= tex_csr_if.write_data;
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`CSR_TEX0_STRIDE : tex_stride[0] <= tex_csr_if.write_data;
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`CSR_TEX0_WRAP_U : tex_wrap_u[0] <= tex_csr_if.write_data;
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`CSR_TEX0_WRAP_V : tex_wrap_v[0] <= tex_csr_if.write_data;
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`CSR_TEX0_MIN_FILTER : tex_min_filter[0] <= tex_csr_if.write_data;
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`CSR_TEX0_MAX_FILTER : tex_max_filter[0] <= tex_csr_if.write_data;
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`CSR_TEX1_ADDR : tex_addr[1] <= tex_csr_if.write_data;
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`CSR_TEX1_FORMAT : tex_format[1] <= tex_csr_if.write_data;
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`CSR_TEX1_WIDTH : tex_width[1] <= tex_csr_if.write_data;
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`CSR_TEX1_HEIGHT : tex_height[1] <= tex_csr_if.write_data;
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`CSR_TEX1_STRIDE : tex_stride[1] <= tex_csr_if.write_data;
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`CSR_TEX1_WRAP_U : tex_wrap_u[1] <= tex_csr_if.write_data;
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`CSR_TEX1_WRAP_V : tex_wrap_v[1] <= tex_csr_if.write_data;
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`CSR_TEX1_MIN_FILTER : tex_min_filter[1] <= tex_csr_if.write_data;
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`CSR_TEX1_MAX_FILTER : tex_max_filter[1] <= tex_csr_if.write_data;
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default:
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assert(tex_csr_if.write_addr > `CSR_TEX_END || tex_csr_if.write_addr < `CSR_TEX_BEGIN) else $error("%t: invalid CSR write address: %0h", $time, tex_csr_if.write_addr);
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endcase
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end
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign tex_rsp_if.data[i] = 32'hFAAF;
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end
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assign tex_rsp_if.ready = 1'b1;
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`ifdef DBG_PRINT_TEX_CSRS
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always @(posedge clk) begin
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if (tex_csr_if.write_addr <= `CSR_TEX_END || tex_csr_if.write_addr >= `CSR_TEX_BEGIN) begin
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$display("%t: core%0d-tex_csr: csr_tex0_addr, csr_data=%0h", $time, CORE_ID, tex_addr[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_format, csr_data=%0h", $time, CORE_ID, tex_format[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_width, csr_data=%0h", $time, CORE_ID, tex_width[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_height, csr_data=%0h", $time, CORE_ID, tex_height[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_stride, csr_data=%0h", $time, CORE_ID, tex_stride[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_wrap_u, csr_data=%0h", $time, CORE_ID, tex_wrap_u[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_wrap_v, csr_data=%0h", $time, CORE_ID, tex_wrap_v[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_min_filter, csr_data=%0h", $time, CORE_ID, tex_min_filter[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_max_filter, csr_data=%0h", $time, CORE_ID, tex_max_filter[0]);
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end
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end
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`endif
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endmodule |