20 lines
473 B
Verilog
20 lines
473 B
Verilog
`ifndef VX_TEX_CSR_IF
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`define VX_TEX_CSR_IF
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`include "VX_define.vh"
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interface VX_tex_csr_if ();
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// wire read_enable;
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// wire[`CSR_ADDR_BITS-1:0] read_addr;
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// wire[`NW_BITS-1:0] read_wid;
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// wire[31:0] read_data;
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wire write_enable;
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wire[`CSR_ADDR_BITS-1:0] write_addr;
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// wire[`NW_BITS-1:0] write_wid;
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wire[`CSR_WIDTH-1:0] write_data;
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endinterface
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`endif |