69 lines
1.7 KiB
Verilog
69 lines
1.7 KiB
Verilog
`include "VX_define.vh"
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module VX_warp (
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input wire clk,
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input wire reset,
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input wire stall,
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input wire remove,
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input wire[`NUM_THREADS-1:0] thread_mask,
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input wire change_mask,
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input wire jal,
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input wire[31:0] jal_dest,
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input wire branch_dir,
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input wire[31:0] branch_dest,
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input wire wspawn,
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input wire[31:0] wspawn_pc,
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output wire[31:0] PC,
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output wire[`NUM_THREADS-1:0] valid
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);
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reg [`NUM_THREADS-1:0] valid_t;
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reg [31:0] real_PC;
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reg [31:0] temp_PC;
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reg [31:0] use_PC;
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always @(posedge clk) begin
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if (reset) begin
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valid_t <= {{(`NUM_THREADS-1){1'b0}},1'b1}; // Thread 1 active
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end else if (remove) begin
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valid_t <= 0;
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end else if (change_mask) begin
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valid_t <= thread_mask;
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end
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end
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genvar i;
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generate
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for (i = 0; i < `NUM_THREADS; i++) begin : valid_assign
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assign valid[i] = change_mask ? thread_mask[i] : stall ? 1'b0 : valid_t[i];
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end
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endgenerate
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always @(*) begin
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if (jal == 1'b1) begin
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temp_PC = jal_dest;
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end else if (branch_dir) begin
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temp_PC = branch_dest;
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end else begin
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temp_PC = real_PC;
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end
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end
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assign use_PC = temp_PC;
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assign PC = temp_PC;
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always @(posedge clk) begin
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if (reset) begin
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real_PC <= 0;
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end else if (wspawn) begin
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real_PC <= wspawn_pc;
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end else if (!stall) begin
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real_PC <= use_PC + 32'h4;
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end else begin
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real_PC <= use_PC;
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end
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end
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endmodule |