21 lines
354 B
Verilog
21 lines
354 B
Verilog
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`ifndef VX_DEFINE_SYNTH
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`define VX_DEFINE_SYNTH
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`define NT 8
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`define NW 8
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`define NUMBER_CORES_PER_CLUSTER 1
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`define NUMBER_CLUSTERS 1
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`define DCACHE_SIZE_BYTES 4096
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`define ICACHE_SIZE_BYTES 1024
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// L2 Cache size
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`define LLCACHE_SIZE_BYTES 8192
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// `define QUEUE_FORCE_MLAB 1
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// Use l3 cache (required for cluster behavior)
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// `define L3C 1
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`endif
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