344 lines
16 KiB
Verilog
344 lines
16 KiB
Verilog
`include "VX_define.vh"
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`include "VX_cache_config.vh"
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module Vortex_Cluster #(
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parameter CLUSTER_ID = 0
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) (
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// Clock
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input wire clk,
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input wire reset,
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// IO
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output wire[`NUM_CORES-1:0] io_valid,
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output wire[`NUM_CORES-1:0][31:0] io_data,
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// DRAM Req
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output wire dram_req_read,
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output wire dram_req_write,
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output wire[`L2DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire[`L2DRAM_LINE_WIDTH-1:0] dram_req_data,
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output wire[`L2DRAM_TAG_WIDTH-1:0] dram_req_tag,
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input wire dram_req_ready,
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// DRAM Rsp
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input wire dram_rsp_valid,
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input wire[`L2DRAM_LINE_WIDTH-1:0] dram_rsp_data,
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input wire[`L2DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
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output wire dram_rsp_ready,
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// LLC Snooping
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input wire llc_snp_req_valid,
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input wire[`L2DRAM_ADDR_WIDTH-1:0] llc_snp_req_addr,
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output wire llc_snp_req_ready,
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output wire ebreak
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);
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if (`NUM_CORES == 1) begin
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VX_cache_dram_req_if #(
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.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
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.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
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.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
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) dcache_dram_req_if();
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VX_cache_dram_rsp_if #(
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.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
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.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
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) dcache_dram_rsp_if();
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VX_cache_dram_req_if #(
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.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
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.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
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.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
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) icache_dram_req_if();
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VX_cache_dram_rsp_if #(
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.DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH),
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.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
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) icache_dram_rsp_if();
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VX_cache_dram_req_if #(
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.DRAM_LINE_WIDTH(`L2DRAM_LINE_WIDTH),
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.DRAM_ADDR_WIDTH(`L2DRAM_ADDR_WIDTH),
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.DRAM_TAG_WIDTH(`L2DRAM_TAG_WIDTH)
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) dram_req_if();
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VX_cache_dram_rsp_if #(
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.DRAM_LINE_WIDTH(`L2DRAM_LINE_WIDTH),
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.DRAM_TAG_WIDTH(`L2DRAM_TAG_WIDTH)
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) dram_rsp_if();
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assign dram_req_read = dram_req_if.dram_req_read;
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assign dram_req_write = dram_req_if.dram_req_write;
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assign dram_req_addr = dram_req_if.dram_req_addr;
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assign dram_req_data = dram_req_if.dram_req_data;
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assign dram_req_tag = dram_req_if.dram_req_tag;
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assign dram_req_if.dram_req_ready = dram_req_ready;
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assign dram_rsp_if.dram_rsp_valid = dram_rsp_valid;
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assign dram_rsp_if.dram_rsp_data = dram_rsp_data;
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assign dram_rsp_if.dram_rsp_tag = dram_rsp_tag;
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assign dram_rsp_ready = dram_rsp_if.dram_rsp_ready;
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VX_l1c_to_dram_arb #(
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.REQQ_SIZE(`L2REQQ_SIZE)
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) l1c_to_dram_arb (
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.clk (clk),
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.reset (reset),
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.dcache_dram_req_if (dcache_dram_req_if),
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.dcache_dram_rsp_if (dcache_dram_rsp_if),
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.icache_dram_req_if (icache_dram_req_if),
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.icache_dram_rsp_if (icache_dram_rsp_if),
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.dram_req_if (dram_req_if),
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.dram_rsp_if (dram_rsp_if)
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);
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Vortex #(
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.CORE_ID(0)
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) vortex_core (
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.clk (clk),
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.reset (reset),
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.io_valid (io_valid[0]),
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.io_data (io_data[0]),
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.D_dram_req_read (dcache_dram_req_if.dram_req_read),
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.D_dram_req_write (dcache_dram_req_if.dram_req_write),
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.D_dram_req_addr (dcache_dram_req_if.dram_req_addr),
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.D_dram_req_data (dcache_dram_req_if.dram_req_data),
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.D_dram_req_tag (dcache_dram_req_if.dram_req_tag),
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.D_dram_req_ready (dcache_dram_req_if.dram_req_ready),
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.D_dram_rsp_valid (dcache_dram_rsp_if.dram_rsp_valid),
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.D_dram_rsp_data (dcache_dram_rsp_if.dram_rsp_data),
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.D_dram_rsp_tag (dcache_dram_rsp_if.dram_rsp_tag),
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.D_dram_rsp_ready (dcache_dram_rsp_if.dram_rsp_ready),
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.I_dram_req_read (icache_dram_req_if.dram_req_read),
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.I_dram_req_write (icache_dram_req_if.dram_req_write),
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.I_dram_req_addr (icache_dram_req_if.dram_req_addr),
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.I_dram_req_data (icache_dram_req_if.dram_req_data),
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.I_dram_req_tag (icache_dram_req_if.dram_req_tag),
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.I_dram_req_ready (icache_dram_req_if.dram_req_ready),
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.I_dram_rsp_valid (icache_dram_rsp_if.dram_rsp_valid),
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.I_dram_rsp_data (icache_dram_rsp_if.dram_rsp_data),
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.I_dram_rsp_ready (icache_dram_rsp_if.dram_rsp_ready),
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.I_dram_rsp_tag (icache_dram_rsp_if.dram_rsp_tag),
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.llc_snp_req_valid (llc_snp_req_valid),
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.llc_snp_req_addr (llc_snp_req_addr),
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.llc_snp_req_ready (llc_snp_req_ready),
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.ebreak (ebreak)
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);
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end else begin
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// DRAM Dcache Req
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wire[`NUM_CORES-1:0] per_core_D_dram_req_read;
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wire[`NUM_CORES-1:0] per_core_D_dram_req_write;
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wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_D_dram_req_addr;
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wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_req_data;
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wire[`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_req_tag;
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// DRAM Dcache Rsp
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wire[`NUM_CORES-1:0] per_core_D_dram_rsp_valid;
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wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_rsp_data;
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wire[`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_rsp_tag;
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wire[`NUM_CORES-1:0] per_core_D_dram_rsp_ready;
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// DRAM Icache Req
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wire[`NUM_CORES-1:0] per_core_I_dram_req_read;
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wire[`NUM_CORES-1:0] per_core_I_dram_req_write;
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wire[`NUM_CORES-1:0][`IDRAM_ADDR_WIDTH-1:0] per_core_I_dram_req_addr;
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wire[`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_req_data;
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wire[`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_req_tag;
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// DRAM Icache Rsp
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wire[`NUM_CORES-1:0] per_core_I_dram_rsp_valid;
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wire[`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_rsp_data;
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wire[`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_rsp_tag;
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wire[`NUM_CORES-1:0] per_core_I_dram_rsp_ready;
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// Out ebreak
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wire[`NUM_CORES-1:0] per_core_ebreak;
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wire[`NUM_CORES-1:0] per_core_io_valid;
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wire[`NUM_CORES-1:0][31:0] per_core_io_data;
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wire l2_core_req_ready;
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wire snp_fwd_valid;
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wire[`DDRAM_ADDR_WIDTH-1:0] snp_fwd_addr;
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wire[`NUM_CORES-1:0] per_core_snp_fwd_ready;
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assign ebreak = (& per_core_ebreak);
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genvar i;
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for (i = 0; i < `NUM_CORES; i = i + 1) begin
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wire [`IDRAM_LINE_WIDTH-1:0] curr_core_D_dram_req_data;
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wire [`DDRAM_LINE_WIDTH-1:0] curr_core_I_dram_req_data;
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assign io_valid[i] = per_core_io_valid[i];
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assign io_data[i] = per_core_io_data[i];
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Vortex #(
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.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
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) vortex_core (
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.clk (clk),
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.reset (reset),
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.io_valid (per_core_io_valid [i]),
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.io_data (per_core_io_data [i]),
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.D_dram_req_read (per_core_D_dram_req_read [i]),
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.D_dram_req_write (per_core_D_dram_req_write [i]),
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.D_dram_req_addr (per_core_D_dram_req_addr [i]),
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.D_dram_req_data (curr_core_D_dram_req_data ),
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.D_dram_req_tag (per_core_D_dram_req_tag [i]),
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.D_dram_req_ready (l2_core_req_ready ),
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.D_dram_rsp_valid (per_core_D_dram_rsp_valid [i]),
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.D_dram_rsp_data (per_core_D_dram_rsp_data [i]),
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.D_dram_rsp_tag (per_core_D_dram_rsp_tag [i]),
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.D_dram_rsp_ready (per_core_D_dram_rsp_ready [i]),
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.I_dram_req_read (per_core_I_dram_req_read [i]),
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.I_dram_req_write (per_core_I_dram_req_write [i]),
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.I_dram_req_addr (per_core_I_dram_req_addr [i]),
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.I_dram_req_data (curr_core_I_dram_req_data ),
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.I_dram_req_tag (per_core_I_dram_req_tag [i]),
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.I_dram_req_ready (l2_core_req_ready ),
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.I_dram_rsp_valid (per_core_I_dram_rsp_valid [i]),
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.I_dram_rsp_tag (per_core_I_dram_rsp_tag [i]),
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.I_dram_rsp_data (per_core_I_dram_rsp_data [i]),
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.I_dram_rsp_ready (per_core_I_dram_rsp_ready [i]),
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.llc_snp_req_valid (snp_fwd_valid),
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.llc_snp_req_addr (snp_fwd_addr),
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.llc_snp_req_ready (per_core_snp_fwd_ready [i]),
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.ebreak (per_core_ebreak [i])
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);
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assign per_core_D_dram_req_data [i] = curr_core_D_dram_req_data;
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assign per_core_I_dram_req_data [i] = curr_core_I_dram_req_data;
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end
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// L2 Cache ///////////////////////////////////////////////////////////
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wire[`L2NUM_REQUESTS-1:0] l2_core_req_valid;
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wire[`L2NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l2_core_req_mem_write;
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wire[`L2NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l2_core_req_mem_read;
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wire[`L2NUM_REQUESTS-1:0][31:0] l2_core_req_addr;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] l2_core_req_tag;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] l2_core_req_data;
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wire[`L2NUM_REQUESTS-1:0] l2_core_rsp_valid;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] l2_core_rsp_data;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] l2_core_rsp_tag;
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wire[`L2NUM_REQUESTS-1:0] l2_core_rsp_ready;
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wire[`DDRAM_LINE_WIDTH-1:0] l2_dram_req_data;
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wire[`DDRAM_LINE_WIDTH-1:0] l2_dram_rsp_data;
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assign dram_req_data = l2_dram_req_data;
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assign l2_dram_rsp_data = dram_rsp_data;
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for (i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin
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// Core Request
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assign l2_core_req_valid [i] = (per_core_D_dram_req_read[(i/2)] | per_core_D_dram_req_write[(i/2)]);
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assign l2_core_req_valid [i+1] = (per_core_I_dram_req_read[(i/2)] | per_core_I_dram_req_write[(i/2)]);
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assign l2_core_req_mem_write [i] = per_core_D_dram_req_write[(i/2)] ? `WORD_SEL_LW : `WORD_SEL_NO;
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assign l2_core_req_mem_write [i+1] = `WORD_SEL_NO;
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assign l2_core_req_mem_read [i] = per_core_D_dram_req_read[(i/2)] ? `WORD_SEL_LW : `WORD_SEL_NO;
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assign l2_core_req_mem_read [i+1] = `WORD_SEL_NO;
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assign l2_core_req_addr [i] = {per_core_D_dram_req_addr[(i/2)], {`LOG2UP(`DBANK_LINE_SIZE){1'b0}}};
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assign l2_core_req_addr [i+1] = {per_core_I_dram_req_addr[(i/2)], {`LOG2UP(`IBANK_LINE_SIZE){1'b0}}};
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assign l2_core_req_data [i] = per_core_D_dram_req_data[(i/2)];
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assign l2_core_req_data [i+1] = per_core_I_dram_req_data[(i/2)];
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assign l2_core_req_tag [i] = per_core_D_dram_req_tag[(i/2)];
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assign l2_core_req_tag [i+1] = per_core_I_dram_req_tag[(i/2)];
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assign per_core_D_dram_rsp_valid [(i/2)] = l2_core_rsp_valid[i];
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assign per_core_I_dram_rsp_valid [(i/2)] = l2_core_rsp_valid[i+1];
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assign per_core_D_dram_rsp_data [(i/2)] = l2_core_rsp_data[i];
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assign per_core_I_dram_rsp_data [(i/2)] = l2_core_rsp_data[i+1];
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assign per_core_D_dram_rsp_tag [(i/2)] = l2_core_rsp_tag[i];
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assign per_core_I_dram_rsp_tag [(i/2)] = l2_core_rsp_tag[i+1];
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assign l2_core_rsp_ready [i] = per_core_D_dram_rsp_ready [(i/2)];
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assign l2_core_rsp_ready [i+1] = per_core_I_dram_rsp_ready[(i/2)];
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end
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VX_cache #(
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.CACHE_SIZE (`L2CACHE_SIZE),
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.BANK_LINE_SIZE (`L2BANK_LINE_SIZE),
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.NUM_BANKS (`L2NUM_BANKS),
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.WORD_SIZE (`L2WORD_SIZE),
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.NUM_REQUESTS (`L2NUM_REQUESTS),
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.STAGE_1_CYCLES (`L2STAGE_1_CYCLES),
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.FUNC_ID (`L2FUNC_ID),
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.REQQ_SIZE (`L2REQQ_SIZE),
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.MRVQ_SIZE (`L2MRVQ_SIZE),
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.DFPQ_SIZE (`L2DFPQ_SIZE),
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.SNRQ_SIZE (`L2SNRQ_SIZE),
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.CWBQ_SIZE (`L2CWBQ_SIZE),
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.DWBQ_SIZE (`L2DWBQ_SIZE),
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.DFQQ_SIZE (`L2DFQQ_SIZE),
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.LLVQ_SIZE (`L2LLVQ_SIZE),
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.FFSQ_SIZE (`L2FFSQ_SIZE),
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.PRFQ_SIZE (`L2PRFQ_SIZE),
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.PRFQ_STRIDE (`L2PRFQ_STRIDE),
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.FILL_INVALIDAOR_SIZE (`L2FILL_INVALIDAOR_SIZE),
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.CORE_TAG_WIDTH (`DDRAM_TAG_WIDTH),
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.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH)
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) gpu_l2cache (
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valid (l2_core_req_valid),
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.core_req_read (l2_core_req_mem_read),
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.core_req_write (l2_core_req_mem_write),
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.core_req_addr (l2_core_req_addr),
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.core_req_data (l2_core_req_data),
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.core_req_tag (l2_core_req_tag),
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.core_req_ready (l2_core_req_ready),
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// Core response
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.core_rsp_valid (l2_core_rsp_valid),
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.core_rsp_data (l2_core_rsp_data),
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.core_rsp_tag (l2_core_rsp_tag),
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.core_rsp_ready (|l2_core_rsp_ready),
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// DRAM request
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.dram_req_read (dram_req_read),
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.dram_req_write (dram_req_write),
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.dram_req_addr (dram_req_addr),
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.dram_req_data (l2_dram_req_data),
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.dram_req_tag (dram_req_tag),
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.dram_req_ready (dram_req_ready),
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// L2 Cache DRAM Fill response
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.dram_rsp_valid (dram_rsp_valid),
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.dram_rsp_tag (dram_rsp_tag),
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.dram_rsp_data (l2_dram_rsp_data),
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.dram_rsp_ready (dram_rsp_ready),
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// Snoop request
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.snp_req_valid (llc_snp_req_valid),
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.snp_req_addr (llc_snp_req_addr),
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.snp_req_ready (llc_snp_req_ready),
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// Snoop forwarding
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.snp_fwd_valid (snp_fwd_valid),
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.snp_fwd_addr (snp_fwd_addr),
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.snp_fwd_ready (& per_core_snp_fwd_ready)
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);
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end
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endmodule |