245 lines
8.7 KiB
Verilog
245 lines
8.7 KiB
Verilog
`include "VX_define.vh"
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`include "VX_cache_config.vh"
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module Vortex #(
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parameter CORE_ID = 0
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) (
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// Clock
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid,
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output wire [31:0] io_data,
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// DRAM Dcache Req
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output wire D_dram_req_read,
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output wire D_dram_req_write,
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output wire [`DDRAM_ADDR_WIDTH-1:0] D_dram_req_addr,
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output wire [`DDRAM_LINE_WIDTH-1:0] D_dram_req_data,
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output wire [`DDRAM_TAG_WIDTH-1:0] D_dram_req_tag,
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input wire D_dram_req_ready,
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// DRAM Dcache Rsp
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input wire D_dram_rsp_valid,
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input wire [`DDRAM_LINE_WIDTH-1:0] D_dram_rsp_data,
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input wire [`DDRAM_TAG_WIDTH-1:0] D_dram_rsp_tag,
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output wire D_dram_rsp_ready,
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// DRAM Icache Req
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output wire I_dram_req_read,
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output wire I_dram_req_write,
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output wire [`IDRAM_ADDR_WIDTH-1:0] I_dram_req_addr,
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output wire [`IDRAM_LINE_WIDTH-1:0] I_dram_req_data,
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output wire [`IDRAM_TAG_WIDTH-1:0] I_dram_req_tag,
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input wire I_dram_req_ready,
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// DRAM Icache Rsp
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input wire I_dram_rsp_valid,
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input wire [`IDRAM_LINE_WIDTH-1:0] I_dram_rsp_data,
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input wire [`IDRAM_TAG_WIDTH-1:0] I_dram_rsp_tag,
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output wire I_dram_rsp_ready,
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// LLC Snooping
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input wire llc_snp_req_valid,
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input wire [`DDRAM_ADDR_WIDTH-1:0] llc_snp_req_addr,
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output wire llc_snp_req_ready,
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output wire ebreak
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);
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`DEBUG_BEGIN
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wire scheduler_empty;
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`DEBUG_END
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wire memory_delay;
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wire exec_delay;
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wire gpr_stage_delay;
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wire schedule_delay;
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// Dcache Interfaces
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VX_cache_core_req_if #(
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.NUM_REQUESTS(`DNUM_REQUESTS),
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.WORD_SIZE(`DWORD_SIZE),
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.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
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) dcache_core_req_if();
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VX_cache_core_req_if #(
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.NUM_REQUESTS(`DNUM_REQUESTS),
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.WORD_SIZE(`DWORD_SIZE),
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.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
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) dcache_core_req_qual_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS(`DNUM_REQUESTS),
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.WORD_SIZE(`DWORD_SIZE),
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.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
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) dcache_core_rsp_if();
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VX_cache_dram_req_if #(
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.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
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.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
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.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
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) dcache_dram_req_if();
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VX_cache_dram_rsp_if #(
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.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
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.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
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) dcache_dram_rsp_if();
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assign D_dram_req_write = dcache_dram_req_if.dram_req_write;
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assign D_dram_req_read = dcache_dram_req_if.dram_req_read;
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assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr;
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assign D_dram_req_data = dcache_dram_req_if.dram_req_data;
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assign D_dram_req_tag = dcache_dram_req_if.dram_req_tag;
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assign dcache_dram_req_if.dram_req_ready = D_dram_req_ready;
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assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid;
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assign dcache_dram_rsp_if.dram_rsp_data = D_dram_rsp_data;
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assign dcache_dram_rsp_if.dram_rsp_tag = D_dram_rsp_tag;
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assign D_dram_rsp_ready = dcache_dram_rsp_if.dram_rsp_ready;
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assign io_valid = (!memory_delay)
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&& (|dcache_core_req_if.core_req_valid)
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&& (dcache_core_req_if.core_req_write[0] != `WORD_SEL_NO)
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&& (dcache_core_req_if.core_req_addr[0] == `IO_BUS_ADDR);
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assign io_data = dcache_core_req_if.core_req_data[0];
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assign dcache_core_req_qual_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{~io_valid}};
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assign dcache_core_req_qual_if.core_req_read = dcache_core_req_if.core_req_read;
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assign dcache_core_req_qual_if.core_req_write = dcache_core_req_if.core_req_write;
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assign dcache_core_req_qual_if.core_req_addr = dcache_core_req_if.core_req_addr;
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assign dcache_core_req_qual_if.core_req_data = dcache_core_req_if.core_req_data;
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assign dcache_core_req_qual_if.core_req_tag = dcache_core_req_if.core_req_tag;
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assign dcache_core_req_if.core_req_ready = dcache_core_req_qual_if.core_req_ready;
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// Icache interfaces
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VX_cache_core_req_if #(
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.NUM_REQUESTS(`INUM_REQUESTS),
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.WORD_SIZE(`IWORD_SIZE),
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.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
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) icache_core_req_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS(`INUM_REQUESTS),
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.WORD_SIZE(`IWORD_SIZE),
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.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
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) icache_core_rsp_if();
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VX_cache_dram_req_if #(
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.DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH),
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.DRAM_ADDR_WIDTH(`IDRAM_ADDR_WIDTH),
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.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
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) icache_dram_req_if();
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VX_cache_dram_rsp_if #(
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.DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH),
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.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
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) icache_dram_rsp_if();
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assign I_dram_req_write = icache_dram_req_if.dram_req_write;
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assign I_dram_req_read = icache_dram_req_if.dram_req_read;
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assign I_dram_req_addr = icache_dram_req_if.dram_req_addr;
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assign I_dram_req_data = icache_dram_req_if.dram_req_data;
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assign I_dram_req_tag = icache_dram_req_if.dram_req_tag;
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assign icache_dram_req_if.dram_req_ready = I_dram_req_ready;
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assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid;
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assign icache_dram_rsp_if.dram_rsp_data = I_dram_rsp_data;
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assign icache_dram_rsp_if.dram_rsp_tag = I_dram_rsp_tag;
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assign I_dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready;
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///////////////////////////////////////////////////////////////////////////////
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// Front-end to Back-end
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VX_frE_to_bckE_req_if bckE_req_if(); // New instruction request to EXE/MEM
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// Back-end to Front-end
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VX_wb_if writeback_if(); // Writeback to GPRs
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VX_branch_rsp_if branch_rsp_if(); // Branch Resolution to Fetch
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VX_jal_rsp_if jal_rsp_if(); // Jump resolution to Fetch
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// Warp controls
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VX_warp_ctl_if warp_ctl_if();
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// Cache snooping
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VX_cache_snp_req_if #(.DRAM_ADDR_WIDTH(`IDRAM_ADDR_WIDTH)) icache_snp_req_if();
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VX_cache_snp_req_if #(.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH)) dcache_snp_req_if();
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assign dcache_snp_req_if.snp_req_valid = llc_snp_req_valid;
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assign dcache_snp_req_if.snp_req_addr = llc_snp_req_addr;
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assign llc_snp_req_ready = dcache_snp_req_if.snp_req_ready;
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VX_front_end front_end (
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.clk (clk),
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.reset (reset),
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.warp_ctl_if (warp_ctl_if),
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.bckE_req_if (bckE_req_if),
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.schedule_delay (schedule_delay),
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.icache_rsp_if (icache_core_rsp_if),
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.icache_req_if (icache_core_req_if),
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.jal_rsp_if (jal_rsp_if),
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.branch_rsp_if (branch_rsp_if),
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.fetch_ebreak (ebreak)
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);
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VX_scheduler scheduler (
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.clk (clk),
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.reset (reset),
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.memory_delay (memory_delay),
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.exec_delay (exec_delay),
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.gpr_stage_delay(gpr_stage_delay),
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.bckE_req_if (bckE_req_if),
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.writeback_if (writeback_if),
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.schedule_delay (schedule_delay),
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.is_empty (scheduler_empty)
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);
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VX_back_end #(
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.CORE_ID(CORE_ID)
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) back_end (
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.clk (clk),
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.reset (reset),
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.schedule_delay (schedule_delay),
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.warp_ctl_if (warp_ctl_if),
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.bckE_req_if (bckE_req_if),
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.jal_rsp_if (jal_rsp_if),
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.branch_rsp_if (branch_rsp_if),
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.dcache_rsp_if (dcache_core_rsp_if),
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.dcache_req_if (dcache_core_req_if),
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.writeback_if (writeback_if),
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.mem_delay (memory_delay),
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.exec_delay (exec_delay),
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.gpr_stage_delay (gpr_stage_delay)
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);
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VX_dmem_ctrl dmem_ctrl (
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.clk (clk),
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.reset (reset),
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// Dram <-> Dcache
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.dcache_dram_req_if (dcache_dram_req_if),
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.dcache_dram_rsp_if (dcache_dram_rsp_if),
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.dcache_snp_req_if (dcache_snp_req_if),
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// Dram <-> Icache
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.icache_dram_req_if (icache_dram_req_if),
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.icache_dram_rsp_if (icache_dram_rsp_if),
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.icache_snp_req_if (icache_snp_req_if),
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// Core <-> Icache
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.icache_core_req_if (icache_core_req_if),
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.icache_core_rsp_if (icache_core_rsp_if),
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// Core <-> Dcache
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.dcache_core_req_if (dcache_core_req_qual_if),
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.dcache_core_rsp_if (dcache_core_rsp_if)
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);
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endmodule // Vortex
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