100 lines
3.3 KiB
Verilog
100 lines
3.3 KiB
Verilog
`include "VX_define.vh"
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module VX_fetch (
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input wire clk,
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input wire reset,
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VX_wstall_if wstall_if,
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VX_join_if join_if,
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input wire schedule_delay,
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input wire icache_stage_delay,
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input wire[`NW_BITS-1:0] icache_stage_wid,
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input wire[`NUM_THREADS-1:0] icache_stage_valids,
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output wire ebreak,
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VX_jal_rsp_if jal_rsp_if,
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VX_branch_rsp_if branch_rsp_if,
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VX_inst_meta_if fe_inst_meta_fi,
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VX_warp_ctl_if warp_ctl_if
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);
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wire[`NUM_THREADS-1:0] thread_mask;
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wire[`NW_BITS-1:0] warp_num;
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wire[31:0] warp_pc;
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wire scheduled_warp;
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wire pipe_stall = schedule_delay || icache_stage_delay;
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VX_warp_sched warp_sched (
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.clk (clk),
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.reset (reset),
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.stall (pipe_stall),
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.is_barrier (warp_ctl_if.is_barrier),
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.barrier_id (warp_ctl_if.barrier_id),
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.num_warps (warp_ctl_if.num_warps),
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.barrier_warp_num (warp_ctl_if.warp_num),
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// Wspawn
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.wspawn (warp_ctl_if.wspawn),
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.wsapwn_pc (warp_ctl_if.wspawn_pc),
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.wspawn_new_active(warp_ctl_if.wspawn_new_active),
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// CTM
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.ctm (warp_ctl_if.change_mask),
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.ctm_mask (warp_ctl_if.thread_mask),
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.ctm_warp_num (warp_ctl_if.warp_num),
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// WHALT
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.whalt (warp_ctl_if.ebreak),
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.whalt_warp_num (warp_ctl_if.warp_num),
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// Wstall
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.wstall (wstall_if.wstall),
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.wstall_warp_num (wstall_if.warp_num),
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// Lock/release Stuff
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.icache_stage_valids(icache_stage_valids),
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.icache_stage_wid (icache_stage_wid),
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// Join
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.is_join (join_if.is_join),
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.join_warp_num (join_if.join_warp_num),
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// Split
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.is_split (warp_ctl_if.is_split),
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.dont_split (warp_ctl_if.dont_split),
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.split_new_mask (warp_ctl_if.split_new_mask),
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.split_later_mask (warp_ctl_if.split_later_mask),
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.split_save_pc (warp_ctl_if.split_save_pc),
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.split_warp_num (warp_ctl_if.warp_num),
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// JAL
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.jal (jal_rsp_if.jal),
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.jal_dest (jal_rsp_if.jal_dest),
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.jal_warp_num (jal_rsp_if.jal_warp_num),
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// Branch
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.branch_valid (branch_rsp_if.valid_branch),
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.branch_dir (branch_rsp_if.branch_dir),
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.branch_dest (branch_rsp_if.branch_dest),
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.branch_warp_num (branch_rsp_if.branch_warp_num),
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// Outputs
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.thread_mask (thread_mask),
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.warp_num (warp_num),
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.warp_pc (warp_pc),
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.ebreak (ebreak),
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.scheduled_warp (scheduled_warp)
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);
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assign fe_inst_meta_fi.warp_num = warp_num;
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assign fe_inst_meta_fi.valid = thread_mask;
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assign fe_inst_meta_fi.instruction = 32'h0;
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assign fe_inst_meta_fi.inst_pc = warp_pc;
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`DEBUG_BEGIN
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wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0);
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wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0);
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`DEBUG_END
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endmodule |