295 lines
13 KiB
Verilog
295 lines
13 KiB
Verilog
`include "VX_define.vh"
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module VX_dmem_ctrl (
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input wire clk,
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input wire reset,
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// Dram <-> Dcache
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VX_cache_dram_req_if dcache_dram_req_if,
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VX_cache_dram_rsp_if dcache_dram_rsp_if,
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VX_cache_snp_req_if dcache_snp_req_if,
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// Dram <-> Icache
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VX_cache_dram_req_if icache_dram_req_if,
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VX_cache_dram_rsp_if icache_dram_rsp_if,
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VX_cache_snp_req_if icache_snp_req_if,
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// Core <-> Dcache
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VX_cache_core_rsp_if dcache_core_rsp_if,
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VX_cache_core_req_if dcache_core_req_if,
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// Core <-> Icache
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VX_cache_core_rsp_if icache_core_rsp_if,
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VX_cache_core_req_if icache_core_req_if
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);
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VX_cache_core_req_if #(
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.NUM_REQUESTS(`DNUM_REQUESTS),
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.WORD_SIZE(`DWORD_SIZE),
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.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
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) dcache_req_smem_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS(`DNUM_REQUESTS),
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.WORD_SIZE(`DWORD_SIZE),
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.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
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) dcache_rsp_smem_if();
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VX_cache_core_req_if #(
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.NUM_REQUESTS(`DNUM_REQUESTS),
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.WORD_SIZE(`DWORD_SIZE),
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.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
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) dcache_req_dcache_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS(`DNUM_REQUESTS),
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.WORD_SIZE(`DWORD_SIZE),
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.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
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) dcache_rsp_dcache_if();
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wire to_shm = `SHARED_MEM_ADDR_MATCH(dcache_core_req_if.core_req_addr[0]);
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wire dcache_wants_wb = (|dcache_rsp_dcache_if.core_rsp_valid);
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// Dcache Request
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assign dcache_req_dcache_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{~to_shm}};
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assign dcache_req_dcache_if.core_req_read = dcache_core_req_if.core_req_read;
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assign dcache_req_dcache_if.core_req_write = dcache_core_req_if.core_req_write;
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assign dcache_req_dcache_if.core_req_addr = dcache_core_req_if.core_req_addr;
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assign dcache_req_dcache_if.core_req_data = dcache_core_req_if.core_req_data;
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assign dcache_req_dcache_if.core_req_tag = dcache_core_req_if.core_req_tag;
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assign dcache_rsp_dcache_if.core_rsp_ready = dcache_core_rsp_if.core_rsp_ready;
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// Shared Memory Request
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assign dcache_req_smem_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{to_shm}};
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assign dcache_req_smem_if.core_req_addr = dcache_core_req_if.core_req_addr;
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assign dcache_req_smem_if.core_req_data = dcache_core_req_if.core_req_data;
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assign dcache_req_smem_if.core_req_read = dcache_core_req_if.core_req_read;
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assign dcache_req_smem_if.core_req_write = dcache_core_req_if.core_req_write;
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assign dcache_req_smem_if.core_req_tag = dcache_core_req_if.core_req_tag;
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assign dcache_core_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready;
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// Dcache Response
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assign dcache_core_rsp_if.core_rsp_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_valid : dcache_rsp_smem_if.core_rsp_valid;
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assign dcache_core_rsp_if.core_rsp_data = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_data : dcache_rsp_smem_if.core_rsp_data;
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assign dcache_core_rsp_if.core_rsp_tag = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_tag : dcache_rsp_smem_if.core_rsp_tag;
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assign dcache_rsp_smem_if.core_rsp_ready = dcache_core_rsp_if.core_rsp_ready && ~dcache_wants_wb;
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VX_cache_dram_req_if #(
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.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
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.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
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.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
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) smem_dram_req_if();
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VX_cache_dram_rsp_if #(
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.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
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.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
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) smem_dram_rsp_if();
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VX_cache #(
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.CACHE_SIZE (`SCACHE_SIZE),
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.BANK_LINE_SIZE (`SBANK_LINE_SIZE),
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.NUM_BANKS (`SNUM_BANKS),
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.WORD_SIZE (`SWORD_SIZE),
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.NUM_REQUESTS (`SNUM_REQUESTS),
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.STAGE_1_CYCLES (`SSTAGE_1_CYCLES),
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.FUNC_ID (`SFUNC_ID),
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.REQQ_SIZE (`SREQQ_SIZE),
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.MRVQ_SIZE (`SMRVQ_SIZE),
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.DFPQ_SIZE (`SDFPQ_SIZE),
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.SNRQ_SIZE (`SSNRQ_SIZE),
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.CWBQ_SIZE (`SCWBQ_SIZE),
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.DWBQ_SIZE (`SDWBQ_SIZE),
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.DFQQ_SIZE (`SDFQQ_SIZE),
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.LLVQ_SIZE (`SLLVQ_SIZE),
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.FFSQ_SIZE (`SFFSQ_SIZE),
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.PRFQ_SIZE (`SPRFQ_SIZE),
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.PRFQ_STRIDE (`SPRFQ_STRIDE),
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.FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE),
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.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
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.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
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) gpu_smem (
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valid (dcache_req_smem_if.core_req_valid),
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.core_req_read (dcache_req_smem_if.core_req_read),
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.core_req_write (dcache_req_smem_if.core_req_write),
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.core_req_addr (dcache_req_smem_if.core_req_addr),
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.core_req_data (dcache_req_smem_if.core_req_data),
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.core_req_tag (dcache_req_smem_if.core_req_tag),
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.core_req_ready (dcache_req_smem_if.core_req_ready),
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// Core response
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.core_rsp_valid (dcache_rsp_smem_if.core_rsp_valid),
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.core_rsp_data (dcache_rsp_smem_if.core_rsp_data),
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.core_rsp_tag (dcache_rsp_smem_if.core_rsp_tag),
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.core_rsp_ready (dcache_rsp_smem_if.core_rsp_ready),
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// DRAM request
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.dram_req_read (smem_dram_req_if.dram_req_read),
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.dram_req_write (smem_dram_req_if.dram_req_write),
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.dram_req_addr (smem_dram_req_if.dram_req_addr),
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.dram_req_data (smem_dram_req_if.dram_req_data),
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.dram_req_tag (smem_dram_req_if.dram_req_tag),
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.dram_req_ready (smem_dram_req_if.dram_req_ready),
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// DRAM response
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.dram_rsp_valid (smem_dram_rsp_if.dram_rsp_valid),
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.dram_rsp_data (smem_dram_rsp_if.dram_rsp_data),
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.dram_rsp_tag (smem_dram_rsp_if.dram_rsp_tag),
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.dram_rsp_ready (smem_dram_rsp_if.dram_rsp_ready),
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// Snoop Request
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.snp_req_valid (0),
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.snp_req_addr (0),
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`IGNORE_WARNINGS_BEGIN
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.snp_req_ready (),
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`IGNORE_WARNINGS_END
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// Snoop Forward
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`IGNORE_WARNINGS_BEGIN
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.snp_fwd_valid (),
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.snp_fwd_addr (),
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`IGNORE_WARNINGS_END
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.snp_fwd_ready (0)
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);
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VX_cache #(
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.CACHE_SIZE (`DCACHE_SIZE),
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.BANK_LINE_SIZE (`DBANK_LINE_SIZE),
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.NUM_BANKS (`DNUM_BANKS),
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.WORD_SIZE (`DWORD_SIZE),
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.NUM_REQUESTS (`DNUM_REQUESTS),
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.STAGE_1_CYCLES (`DSTAGE_1_CYCLES),
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.FUNC_ID (`DFUNC_ID),
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.REQQ_SIZE (`DREQQ_SIZE),
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.MRVQ_SIZE (`DMRVQ_SIZE),
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.DFPQ_SIZE (`DDFPQ_SIZE),
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.SNRQ_SIZE (`DSNRQ_SIZE),
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.CWBQ_SIZE (`DCWBQ_SIZE),
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.DWBQ_SIZE (`DDWBQ_SIZE),
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.DFQQ_SIZE (`DDFQQ_SIZE),
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.LLVQ_SIZE (`DLLVQ_SIZE),
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.FFSQ_SIZE (`DFFSQ_SIZE),
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.PRFQ_SIZE (`DPRFQ_SIZE),
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.PRFQ_STRIDE (`DPRFQ_STRIDE),
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.FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE),
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.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
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.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH)
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) gpu_dcache (
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.clk (clk),
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.reset (reset),
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// Core req
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.core_req_valid (dcache_req_dcache_if.core_req_valid),
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.core_req_read (dcache_req_dcache_if.core_req_read),
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.core_req_write (dcache_req_dcache_if.core_req_write),
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.core_req_addr (dcache_req_dcache_if.core_req_addr),
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.core_req_data (dcache_req_dcache_if.core_req_data),
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.core_req_tag (dcache_req_dcache_if.core_req_tag),
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.core_req_ready (dcache_req_dcache_if.core_req_ready),
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// Core response
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.core_rsp_valid (dcache_rsp_dcache_if.core_rsp_valid),
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.core_rsp_data (dcache_rsp_dcache_if.core_rsp_data),
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.core_rsp_tag (dcache_rsp_dcache_if.core_rsp_tag),
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.core_rsp_ready (dcache_rsp_dcache_if.core_rsp_ready),
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// DRAM request
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.dram_req_read (dcache_dram_req_if.dram_req_read),
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.dram_req_write (dcache_dram_req_if.dram_req_write),
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.dram_req_addr (dcache_dram_req_if.dram_req_addr),
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.dram_req_data (dcache_dram_req_if.dram_req_data),
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.dram_req_tag (dcache_dram_req_if.dram_req_tag),
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.dram_req_ready (dcache_dram_req_if.dram_req_ready),
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// DRAM response
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.dram_rsp_valid (dcache_dram_rsp_if.dram_rsp_valid),
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.dram_rsp_data (dcache_dram_rsp_if.dram_rsp_data),
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.dram_rsp_tag (dcache_dram_rsp_if.dram_rsp_tag),
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.dram_rsp_ready (dcache_dram_rsp_if.dram_rsp_ready),
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// Snoop Request
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.snp_req_valid (dcache_snp_req_if.snp_req_valid),
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.snp_req_addr (dcache_snp_req_if.snp_req_addr),
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.snp_req_ready (dcache_snp_req_if.snp_req_ready),
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// Snoop Forward
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`IGNORE_WARNINGS_BEGIN
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.snp_fwd_valid (),
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.snp_fwd_addr (),
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`IGNORE_WARNINGS_END
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.snp_fwd_ready (0)
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);
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VX_cache #(
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.CACHE_SIZE (`ICACHE_SIZE),
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.BANK_LINE_SIZE (`IBANK_LINE_SIZE),
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.NUM_BANKS (`INUM_BANKS),
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.WORD_SIZE (`IWORD_SIZE),
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.NUM_REQUESTS (`INUM_REQUESTS),
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.STAGE_1_CYCLES (`ISTAGE_1_CYCLES),
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.FUNC_ID (`IFUNC_ID),
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.REQQ_SIZE (`IREQQ_SIZE),
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.MRVQ_SIZE (`IMRVQ_SIZE),
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.DFPQ_SIZE (`IDFPQ_SIZE),
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.SNRQ_SIZE (`ISNRQ_SIZE),
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.CWBQ_SIZE (`ICWBQ_SIZE),
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.DWBQ_SIZE (`IDWBQ_SIZE),
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.DFQQ_SIZE (`IDFQQ_SIZE),
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.LLVQ_SIZE (`ILLVQ_SIZE),
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.FFSQ_SIZE (`IFFSQ_SIZE),
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.PRFQ_SIZE (`IPRFQ_SIZE),
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.PRFQ_STRIDE (`IPRFQ_STRIDE),
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.FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE),
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.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
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.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
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) gpu_icache (
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valid (icache_core_req_if.core_req_valid),
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.core_req_read (icache_core_req_if.core_req_read),
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.core_req_write (icache_core_req_if.core_req_write),
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.core_req_addr (icache_core_req_if.core_req_addr),
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.core_req_data (icache_core_req_if.core_req_data),
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.core_req_tag (icache_core_req_if.core_req_tag),
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.core_req_ready (icache_core_req_if.core_req_ready),
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// Core response
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.core_rsp_valid (icache_core_rsp_if.core_rsp_valid),
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.core_rsp_data (icache_core_rsp_if.core_rsp_data),
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.core_rsp_tag (icache_core_rsp_if.core_rsp_tag),
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.core_rsp_ready (icache_core_rsp_if.core_rsp_ready),
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// DRAM Req
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.dram_req_read (icache_dram_req_if.dram_req_read),
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.dram_req_write (icache_dram_req_if.dram_req_write),
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.dram_req_addr (icache_dram_req_if.dram_req_addr),
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.dram_req_data (icache_dram_req_if.dram_req_data),
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.dram_req_tag (icache_dram_req_if.dram_req_tag),
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.dram_req_ready (icache_dram_req_if.dram_req_ready),
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// DRAM response
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.dram_rsp_valid (icache_dram_rsp_if.dram_rsp_valid),
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.dram_rsp_data (icache_dram_rsp_if.dram_rsp_data),
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.dram_rsp_tag (icache_dram_rsp_if.dram_rsp_tag),
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.dram_rsp_ready (icache_dram_rsp_if.dram_rsp_ready),
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// Snoop Request
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.snp_req_valid (icache_snp_req_if.snp_req_valid),
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.snp_req_addr (icache_snp_req_if.snp_req_addr),
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.snp_req_ready (icache_snp_req_if.snp_req_ready),
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// Snoop Forward
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`IGNORE_WARNINGS_BEGIN
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.snp_fwd_valid (),
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.snp_fwd_addr (),
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`IGNORE_WARNINGS_END
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.snp_fwd_ready (0)
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);
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endmodule
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