c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
65 lines
1.5 KiB
C++
65 lines
1.5 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <iostream>
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#include <vector>
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#define MEM_LATENCY 4
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typedef struct {
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uint8_t valid;
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bool rw;
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uint8_t byteen;
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uint32_t addr;
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uint32_t data;
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uint8_t tag;
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uint8_t ready;
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// Metadata
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uint8_t rsp_sent_mask;
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double cycles_left;
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} req_t;
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typedef struct {
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bool valid;
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uint8_t mask;
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uint32_t data;
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uint8_t tag;
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bool ready;
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} rsp_t;
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class RAM {
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private:
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std::vector<req_t> ram_;
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bool is_rsp_active_;
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bool is_rsp_stall_;
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bool check_duplicate_req(req_t req);
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int simulate_cycle_delay();
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public:
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RAM();
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uint8_t is_ready();
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void insert_req(req_t req);
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rsp_t schedule_rsp();
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void halt_rsp(rsp_t rsp);
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};
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//////////////////////////////////////////////////////
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