Blaise Tine 9f34b2944c code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

..

cache

quartus synthesis build update

2021-04-19 21:29:39 -07:00

core

quartus synthesis build update

2021-04-19 21:29:39 -07:00

fpu_core

adding fpu_core synthesis build

2021-09-05 20:27:55 -07:00

pipeline

minor updates

2021-09-05 23:05:21 -07:00

smem

adding synthesis build for shared memory

2021-05-25 22:02:42 -07:00

top1

quartus synthesis build update

2021-04-19 21:29:39 -07:00

top2

quartus synthesis build update

2021-04-19 21:29:39 -07:00

top4

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

top8

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

top16

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

top32

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

top64

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

unittest

dcache response bus optimization

2021-07-12 10:14:48 -07:00

vortex

Adding Vortex Yosys build support

2021-09-08 23:04:33 -04:00

.gitignore

adding fpu_core synthesis build

2021-09-05 20:27:55 -07:00

Makefile

adding fpu_core synthesis build

2021-09-05 20:27:55 -07:00

project.sdc

minor updates

2021-09-05 23:05:21 -07:00

project.tcl

minor update

2021-07-20 21:42:22 -07:00

timing-html.tcl

performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00