26 lines
397 B
Verilog
26 lines
397 B
Verilog
`ifndef VX_WSTALL_IF
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`define VX_WSTALL_IF
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`include "VX_define.vh"
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interface VX_wstall_if();
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wire valid;
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wire [`NW_BITS-1:0] wid;
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wire stalled;
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modport master (
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output valid,
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output wid,
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output stalled
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);
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modport slave (
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input valid,
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input wid,
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input stalled
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);
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endinterface
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`endif |