26 lines
460 B
Verilog
26 lines
460 B
Verilog
`ifndef VX_GPR_RSP_IF
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`define VX_GPR_RSP_IF
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`include "VX_define.vh"
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interface VX_gpr_rsp_if ();
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wire [`NUM_THREADS-1:0][31:0] rs1_data;
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wire [`NUM_THREADS-1:0][31:0] rs2_data;
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wire [`NUM_THREADS-1:0][31:0] rs3_data;
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modport master (
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output rs1_data,
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output rs2_data,
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output rs3_data
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);
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modport slave (
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input rs1_data,
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input rs2_data,
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input rs3_data
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);
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endinterface
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`endif |