29 lines
486 B
Verilog
29 lines
486 B
Verilog
`ifndef VX_BRANCH_RSP_IF
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`define VX_BRANCH_RSP_IF
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`include "VX_define.vh"
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interface VX_branch_ctl_if ();
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wire valid;
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wire [`NW_BITS-1:0] wid;
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wire taken;
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wire [31:0] dest;
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modport master (
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output valid,
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output wid,
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output taken,
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output dest
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);
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modport slave (
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input valid,
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input wid,
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input taken,
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input dest
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);
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endinterface
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`endif |