83 lines
2.6 KiB
Verilog
83 lines
2.6 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_data_access #(
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parameter CACHE_ID = 0,
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parameter BANK_ID = 0,
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// Size of cache in bytes
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parameter CACHE_SIZE = 1,
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// Size of line inside a bank in bytes
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parameter CACHE_LINE_SIZE = 1,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 1,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Enable write-through
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parameter WRITE_THROUGH = 1
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) (
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input wire clk,
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input wire reset,
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`ifdef DBG_CACHE_REQ_INFO
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`IGNORE_WARNINGS_BEGIN
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input wire[31:0] debug_pc,
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input wire[`NW_BITS-1:0] debug_wid,
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`IGNORE_WARNINGS_END
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`endif
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`IGNORE_WARNINGS_BEGIN
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input wire[`LINE_ADDR_WIDTH-1:0] addr,
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`IGNORE_WARNINGS_END
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// reading
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input wire readen,
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output wire [`CACHE_LINE_WIDTH-1:0] rddata,
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// writing
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input wire writeen,
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input wire is_fill,
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input wire [CACHE_LINE_SIZE-1:0] byteen,
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input wire [`CACHE_LINE_WIDTH-1:0] wrdata
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);
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`UNUSED_VAR (reset)
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wire [CACHE_LINE_SIZE-1:0] byte_enable;
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wire [`LINE_SELECT_BITS-1:0] line_addr = addr[`LINE_SELECT_BITS-1:0];
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VX_sp_ram #(
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.DATAW(CACHE_LINE_SIZE * 8),
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.SIZE(`LINES_PER_BANK),
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.BYTEENW(CACHE_LINE_SIZE),
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.RWCHECK(1)
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) data_store (
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.clk(clk),
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.addr(line_addr),
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.wren(writeen),
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.byteen(byte_enable),
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.rden(1'b1),
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.din(wrdata),
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.dout(rddata)
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);
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assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen;
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`UNUSED_VAR (readen)
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`ifdef DBG_PRINT_CACHE_DATA
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always @(posedge clk) begin
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if (writeen) begin
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if (is_fill) begin
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$display("%t: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, wrdata);
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end else begin
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$display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byte_enable, line_addr, wrdata);
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end
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end
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if (readen) begin
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$display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, rddata);
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end
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end
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`endif
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endmodule |