603 lines
25 KiB
Verilog
603 lines
25 KiB
Verilog
// Cache Memory (8way 4word) //
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// i_ means input port //
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// o_ means output port //
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// _p_ means data exchange with processor //
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// _m_ means data exchange with memory //
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// TO DO:
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// - Send in a response from memory of what the data is from the test bench
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`include "VX_define.v"
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//`include "VX_priority_encoder.v"
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`include "VX_Cache_Bank.v"
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//`include "cache_set.v"
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module VX_d_cache(clk,
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rst,
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i_p_initial_request,
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i_p_addr,
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//i_p_byte_en,
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i_p_writedata,
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i_p_read_or_write, // 0 = Read | 1 = Write
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i_p_valid,
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//i_p_write,
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o_p_readdata,
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o_p_readdata_valid,
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o_p_waitrequest, // 0 = all threads done | 1 = Still threads that need to
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o_m_addr,
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//o_m_byte_en,
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o_m_writedata,
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o_m_read_or_write, // 0 = Read | 1 = Write
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o_m_valid,
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//o_m_write,
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i_m_readdata,
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//i_m_readdata_ready,
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//i_m_waitrequest,
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i_m_ready
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//cnt_r,
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//cnt_w,
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//cnt_hit_r,
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//cnt_hit_w
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//cnt_wb_r,
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//cnt_wb_w
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);
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parameter NUMBER_BANKS = 8;
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localparam CACHE_IDLE = 0; // Idle
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localparam SORT_BY_BANK = 1; // Determines the bank each thread will access
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localparam INITIAL_ACCESS = 2; // Accesses the bank and checks if it is a hit or miss
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localparam INITIAL_PROCESSING = 3; // Check to see if there were misses
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localparam CONTINUED_PROCESSING = 4; // Keep checking status of banks that need to be written back or fetched
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localparam DIRTY_EVICT_GRAB_BLOCK = 5; // Grab the full block of dirty data
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localparam DIRTY_EVICT_WB = 6; // Write back this block into memory
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localparam FETCH_FROM_MEM = 7; // Send a request to mem looking for read data
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localparam FETCH2 = 8; // Stall until memory gets back with the data
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localparam UPDATE_CACHE = 9; // Update the cache with the data read from mem
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localparam RE_ACCESS = 10; // Access the cache after the block has been fetched from memory
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localparam RE_ACCESS_PROCESSING = 11; // Access the cache after the block has been fetched from memory
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//parameter cache_entry = 9;
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input wire clk, rst;
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input wire [`NT_M1:0] i_p_valid;
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//input wire [`NT_M1:0][24:0] i_p_addr; // FIXME
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input wire [`NT_M1:0][31:0] i_p_addr; // FIXME
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input wire i_p_initial_request;
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//input wire [3:0] i_p_byte_en;
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input wire [`NT_M1:0][31:0] i_p_writedata;
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input wire i_p_read_or_write; //, i_p_write;
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output reg [`NT_M1:0][31:0] o_p_readdata;
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output reg [`NT_M1:0] o_p_readdata_valid;
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output wire o_p_waitrequest;
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//output reg [24:0] o_m_addr; // Only one address is sent out at a time to memory -- FIXME
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output reg [31:0] o_m_addr; // Address is xxxxxxxxxxoooobbbyy
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output reg o_m_valid;
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//output wire [255:0][31:0] evicted_data;
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//output wire [3:0] o_m_byte_en;
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//output reg [(NUMBER_BANKS * 32) - 1:0] o_m_writedata;
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output reg[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
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output reg o_m_read_or_write; //, o_m_write;
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//input wire [(NUMBER_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller
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input wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
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//input wire i_m_readdata_ready;
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//input wire i_m_waitrequest;
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input wire i_m_ready;
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//output reg [31:0] cnt_r;
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//output reg [31:0] cnt_w;
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//output reg [31:0] cnt_hit_r;
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//output reg [31:0] cnt_hit_w;
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//output reg [31:0] cnt_wb_r;
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//output reg [31:0] cnt_wb_w;
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//wire [1:0] tag [`NT_M1:0];
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//wire [3:0] index [`NT_M1:0];
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//wire [2:0] bank [`NT_M1:0];
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//wire all_done;
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//integer i;
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reg [`NT_M1:0] thread_done; // Maybe should have "thread_serviced" and "thread_done", serviced==checked cache
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//reg [`NT_M1:0] thread_serviced; // Maybe should have "thread_serviced" and "thread_done", serviced==checked cache
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reg [NUMBER_BANKS - 1:0] banks_ready;
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//reg [NUMBER_BANKS - 1:0] banks_missed;
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reg [NUMBER_BANKS - 1:0] banks_to_service;
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reg [NUMBER_BANKS - 1:0] banks_wb_needed;
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reg [NUMBER_BANKS - 1:0][31:0] banks_wb_addr;
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//reg [NUMBER_BANKS - 1:0] bank_states;
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//reg [NUMBER_BANKS - 1:0][31:0] banks_wb_data;
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//reg [NUMBER_BANKS - 1:0][13:0] banks_in_addr;
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reg [3:0] state;
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reg [NUMBER_BANKS - 1:0][31:0] data_from_bank;
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//reg got_valid_data;
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//reg [31:0] data_to_write;
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//reg [`NT_M1:0] thread_track_bank_0;
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//reg [`NT_M1:0] thread_track_bank_1;
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//reg [`NT_M1:0] thread_track_bank_2;
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//reg [`NT_M1:0] thread_track_bank_3;
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//reg [`NT_M1:0] thread_track_bank_4;
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//reg [`NT_M1:0] thread_track_bank_5;
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//reg [`NT_M1:0] thread_track_bank_6;
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//reg [`NT_M1:0] thread_track_bank_7;
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reg [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks;
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reg [NUMBER_BANKS - 1 : 0] bank_has_access; // Will track if a bank has been accessed in this cycle
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reg [NUMBER_BANKS - 1 : 0][31:0] bank_access_addr;
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reg [NUMBER_BANKS - 1 : 0][31:0] bank_access_data;
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reg [NUMBER_BANKS - 1 : 0][1:0] threads_in_banks;
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//reg [1:0] thread_in_memory; // keeps track of threadID which is in memory
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reg rd_or_wr;
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//reg did_miss, needs_service; Commented out Oct 21
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integer bnk;
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integer found;
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integer t_id;
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//integer num_misses;
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//integer num_evictions_to_wb;
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integer i; //reg [1:0] correct_tag;
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integer index;
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//reg [3:0] correct_index;
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//assign tag = i_p_addr[13:12];
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assign o_p_waitrequest = (thread_done == 4'hF) ? 1'b0 : 1'b1; // change thread_done to be generic
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//assign did_miss = (banks_missed != 8'h0) ? 1'b1 : 1'b0;
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//assign needs_service = ((banks_to_service != 8'b0 || banks_to_service_temp != 8'b0)) ? 1'b1 : 1'b0; // added banks_to_service temp
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//assign w_Test1 = r_Check ? 1'b1 : 1'b0;
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//for ( i = 0;i < `NT_M1;i = i + 1) begin
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// assign tag[i] = i_p_addr[i][13:12];
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// Fares
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// wire no_bank_misses;
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// assign no_bank_misses = banks_to_service != 8'b0;
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reg[NUMBER_BANKS - 1:0] banks_to_service_temp;
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reg[NUMBER_BANKS - 1:0] banks_to_wb;
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reg[NUMBER_BANKS - 1:0] banks_to_wb_temp;
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reg[NUMBER_BANKS - 1:0] banks_all_help;
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always @(posedge clk) begin
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if (rst) begin
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state <= 0;
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//banks_ready <= 8'b0;
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//cnt_r <= 0;
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//cnt_w <= 0;
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//cnt_hit_r <= 0;
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//cnt_hit_w <= 0;
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//cnt_wb_r <= 0;
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//cnt_wb_w <= 0;
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end else begin
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// Change Logic of which state the cache is in
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case (state)
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CACHE_IDLE:begin
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if (i_p_initial_request == 1'b1) begin
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state <= SORT_BY_BANK;
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end else begin
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state <= CACHE_IDLE;
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end
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end
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SORT_BY_BANK:begin
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state <= INITIAL_ACCESS;
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end
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INITIAL_ACCESS:begin
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if (thread_done == 4'hF) begin
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state <= CACHE_IDLE;
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end else begin
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state <= INITIAL_PROCESSING;
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end
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end
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INITIAL_PROCESSING:begin
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if (bank_has_access == banks_ready ) begin // if all hits
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state <= INITIAL_ACCESS;
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end else begin
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state <= CONTINUED_PROCESSING;
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end
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end
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CONTINUED_PROCESSING:begin
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if (banks_to_wb == 8'b0 && banks_to_service == 8'b0) begin // If all threads are done, then the cache can go back into idle state (not currently fetching any requests)
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state <= INITIAL_ACCESS;
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//end else if (num_misses > 0) begin
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end else if ((banks_to_wb != 8'b0)) begin // change 1pm
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state <= DIRTY_EVICT_GRAB_BLOCK;
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//end else if (did_miss == 1'b1 || needs_service == 1'b1) begin
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end else if(banks_to_service != 8'b0) begin
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state <= FETCH_FROM_MEM;
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// end else if (did_miss == 1'b0 && num_evictions_to_wb > 0) begin
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//end else if (needs_service == 1'b0 && did_miss == 1'b0 && (banks_to_wb != 8'b0)) begin
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//end else if (did_miss == 1'b0 && needs_service == 1'b0) begin
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//state <= INITIAL_ACCESS;
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end
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end
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FETCH_FROM_MEM:begin
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state <= FETCH2;
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end
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FETCH2:begin
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if (i_m_ready == 1'b1) begin
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state <= UPDATE_CACHE; // Not sure about this one !!!!!! Check
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end else begin
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state <= FETCH2;
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end
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end
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UPDATE_CACHE:begin
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state <= RE_ACCESS;
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end
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RE_ACCESS:begin
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state <= RE_ACCESS_PROCESSING;
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end
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RE_ACCESS_PROCESSING: begin
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state <= CONTINUED_PROCESSING;
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end
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DIRTY_EVICT_GRAB_BLOCK:begin
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state <= DIRTY_EVICT_WB;
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end
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DIRTY_EVICT_WB:begin
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state <= CONTINUED_PROCESSING;
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end
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endcase
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end
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//tag[`NT_M1:0] <= i_p_addr[`NT_M1:0][13:12];
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end
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// Change values which will be fed into the cache
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always @(*) begin
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case (state)
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CACHE_IDLE:begin
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thread_done = 0;
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o_m_read_or_write = 0;
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o_m_valid = 0;
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o_m_writedata = 0;
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o_p_readdata = 0;
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o_p_readdata_valid = 0;
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bank_has_access = 8'b0;
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//bank_states = CACHE_IDLE;
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//thread_track_bank_0 = 4'b0;
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//thread_track_bank_1 = 4'b0;
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//thread_track_bank_2 = 4'b0;
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//thread_track_bank_3 = 4'b0;
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//thread_track_bank_4 = 4'b0;
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//thread_track_bank_5 = 4'b0;
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//thread_track_bank_6 = 4'b0;
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//thread_track_bank_7 = 4'b0;
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for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
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thread_track_banks[bnk] = 4'b0;
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end
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end
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SORT_BY_BANK:begin
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//bank_states = SORT_BY_BANK;
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rd_or_wr = i_p_read_or_write;
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for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1) begin
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//t_id = {1'b0,t_id};
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if (i_p_valid[t_id] == 1'b0) begin
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thread_done[t_id] = 1'b1;
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end
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//if (i_p_valid[t_id] == 1'b1 && thread_done[t_id] == 1'b0) begin // Need logic for thread done
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else if (i_p_addr[t_id][4:2] == 3'b000) begin
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//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
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//thread_track_bank_0[t_id] = 1'b1;
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thread_track_banks[0][t_id] = 1'b1;
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end
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else if (i_p_addr[t_id][4:2] == 3'b001) begin // !!!!!!!
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//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
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//thread_track_bank_1[t_id] = 1'b1;
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thread_track_banks[1][t_id] = 1'b1;
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end
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else if (i_p_addr[t_id][4:2] == 3'b010) begin
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//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
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//thread_track_bank_2[t_id] = 1'b1;
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thread_track_banks[2][t_id] = 1'b1;
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end
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else if (i_p_addr[t_id][4:2] == 3'b011) begin
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//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
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//thread_track_bank_3[t_id] = 1'b1;
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thread_track_banks[3][t_id] = 1'b1;
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end
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else if (i_p_addr[t_id][4:2] == 3'b100) begin
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//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
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//thread_track_bank_4[t_id] = 1'b1;
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thread_track_banks[4][t_id] = 1'b1;
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end
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else if (i_p_addr[t_id][4:2] == 3'b101) begin
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//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
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//thread_track_bank_5[t_id] = 1'b1;
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thread_track_banks[5][t_id] = 1'b1;
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end
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else if (i_p_addr[t_id][4:2] == 3'b110) begin
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//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
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//thread_track_bank_6[t_id] = 1'b1;
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thread_track_banks[6][t_id] = 1'b1;
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end
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else if (i_p_addr[t_id][4:2] == 3'b111) begin
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//banks_in_addr[0] = i_p_addr[t_id]; // WIll need to do this later
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//thread_track_bank_7[t_id] = 1'b1;
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thread_track_banks[7][t_id] = 1'b1;
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end
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end
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end
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INITIAL_ACCESS:begin
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//bank_states = INITIAL_ACCESS;
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o_m_valid = 1'b0;
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// Before Access
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// if (no_bank_misses) begin
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// Dont do anything, next clock cycle it will switch back to (Fetch from mem)
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// end else begin // Do logic to send requests to each bank (look through thread_track_bank regs)
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bank_has_access = 8'b0;
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for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1) begin
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for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
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if(thread_track_banks[bnk][t_id] == 1'b1 && bank_has_access[bnk] == 1'b0) begin
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bank_has_access[bnk] = 1'b1;
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bank_access_data[bnk] = i_p_writedata[t_id];
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bank_access_addr[bnk] = i_p_addr[t_id];
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threads_in_banks[bnk] = t_id[1:0];
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end
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end
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//if (banks_wb_needed[bnk]) begin // need to fix this for multiple misses
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//o_m_read_or_write = 1'b0;
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//o_m_addr = banks_wb_addr[bnk];
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//o_m_valid = 1'b1;
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//o_m_writedata = {banks_wb_data[bnk], 96'b0};
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//end
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//if(thread_track_bank_0[t_id] == 1'b1 && bank_has_access[0] == 1'b0) begin
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//bank_has_access[0] = 1'b1;
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//bank_access_data[0] = i_p_writedata[t_id];
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//bank_access_addr[0] = i_p_addr[t_id];
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//threads_in_banks[0] = t_id;
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//end
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// NEED TO UPDATE HITS (STORE IN THREADS_DONE)
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end
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//num_misses = {28'b0, $countones(banks_missed)};
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//did_miss = (banks_missed == 4'hF);
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// end
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end
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INITIAL_PROCESSING:begin
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//bank_has_access = 8'b0;
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for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
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if(banks_ready[bnk]) begin // FIX to handle hits
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thread_done[threads_in_banks[bnk]] = 1'b1;
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o_p_readdata[threads_in_banks[bnk]] = data_from_bank[bnk];
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if(i_p_read_or_write == 1'b0) begin
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o_p_readdata_valid[threads_in_banks[bnk]] = 1'b1;
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end
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thread_track_banks[bnk][threads_in_banks[bnk]] = 1'b0; // Update that this thread does not need to be serviced again
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end
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end
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//banks_to_service_temp = !banks_ready; // These are clean misses
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for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
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assign banks_to_service_temp[bnk] = (banks_ready[bnk] || (bank_has_access[bnk] == 0)) ? 1'b0 : 1'b1;
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assign banks_to_wb_temp[bnk] = (banks_wb_needed[bnk]);
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assign banks_all_help[bnk] = banks_to_service_temp[bnk] || banks_to_wb_temp[bnk];
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end
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end
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CONTINUED_PROCESSING:begin
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//for (i = `NW-1; i >= 0; i = i - 1) begin
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// if (thread_done[threads_in_banks[bnk]] == 1'b1) begin // Not sure about this logic
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// //index = i[`NW_M1:0];
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// banks_to_service_temp[i] = 1'b0;
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// banks_to_wb_temp[i] = 1'b0;
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// end
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//end
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end
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FETCH_FROM_MEM:begin
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// NEED TO ADD LOGIC TO SEE IF MISSES GO TO SAME BLOCK
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index = 0;
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found = 0;
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for (i = `NW-1; i >= 0; i = i - 1) begin
|
|
if (banks_to_service[i]) begin // Not sure about this logic
|
|
//index = i[`NW_M1:0];
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|
index = i;
|
|
found = 1;
|
|
end
|
|
end
|
|
if (found == 1) begin
|
|
//banks_missed[index] = 0;
|
|
//thread_done
|
|
|
|
//thread_in_memory = threads_in_banks[index];
|
|
//o_m_writedata = bank_access_data[index];
|
|
banks_to_service_temp[index] = 0;
|
|
o_m_addr = bank_access_addr[index];
|
|
o_m_valid = 1'b1;
|
|
o_m_read_or_write = 1'b0;
|
|
end
|
|
//bank_states = FETCH_FROM_MEM;
|
|
end
|
|
FETCH2:begin
|
|
o_m_valid = 1'b0;
|
|
end
|
|
UPDATE_CACHE:begin
|
|
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
|
//if(thread_track_banks[bnk][t_id] == 1'b1 && bank_has_access[bnk] == 1'b0) begin
|
|
bank_has_access[bnk] = 1'b1;
|
|
//bank_access_data[bnk] = i_m_readdata[(bnk+1)*32 - 1:bnk*32];
|
|
bank_access_addr[bnk] = o_m_addr;
|
|
threads_in_banks[bnk] = t_id[1:0];
|
|
//end
|
|
end
|
|
//bank_access_data = i_m_readdata;
|
|
rd_or_wr = 1'b1;
|
|
//thread_done[thread_in_memory] = 1'b1; // Removed, new cache style - Oct 21
|
|
//o_p_readdata[thread_in_memory] = i_m_readdata[i_p_addr[thread_in_memory][9:5]]; // Removed, new cache style
|
|
end
|
|
DIRTY_EVICT_WB:begin // this begininng logic should be added to dirty evict grab block
|
|
|
|
//thread_done[thread_in_memory] = 1'b1;
|
|
o_m_valid = 1'b1;
|
|
end
|
|
DIRTY_EVICT_GRAB_BLOCK:begin
|
|
index = 0;
|
|
found = 0;
|
|
for (i = `NW-1; i >= 0; i = i - 1) begin
|
|
if (banks_to_wb_temp[i]) begin
|
|
//index = i[`NW_M1:0];
|
|
index = i;
|
|
found = 1;
|
|
end
|
|
end
|
|
if (found == 1) begin
|
|
banks_to_wb_temp[index] = 0;
|
|
for (i = `NW-1; i >= 0; i = i - 1) begin
|
|
if (banks_to_wb_temp[i] && banks_wb_addr[index][31:7] == banks_wb_addr[i][31:7]) begin
|
|
//index = i[`NW_M1:0];
|
|
banks_to_wb_temp[i] = 0;
|
|
end
|
|
end
|
|
//thread_done
|
|
//thread_in_memory = threads_in_banks[index];
|
|
//o_m_writedata[(bnk+1)*32 - 1:bnk*32] = banks_wb_data[index];
|
|
o_m_addr = banks_wb_addr[index];
|
|
o_m_read_or_write = 1'b1;
|
|
end
|
|
//for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
|
//o_m_writedata[(bnk+1)*32 - 1:bnk*32] = banks_wb_data[index];
|
|
//end
|
|
// NEXT LINE CONTAINS DATA TO WB !!!! Think need to just change this to be read data and can remove banks_wb_data
|
|
//o_m_writedata = {banks_wb_data[7],banks_wb_data[6],banks_wb_data[5],banks_wb_data[4],banks_wb_data[3],banks_wb_data[2],banks_wb_data[1],banks_wb_data[0]};
|
|
//num_evictions_to_wb = {28'b0, $countones(banks_wb_needed)};
|
|
rd_or_wr = 1'b0;
|
|
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
|
//if(thread_track_banks[bnk][t_id] == 1'b1 && bank_has_access[bnk] == 1'b0) begin
|
|
bank_has_access[bnk] = 1'b1;
|
|
bank_access_addr[bnk] = o_m_addr;
|
|
//end
|
|
end
|
|
end
|
|
RE_ACCESS:begin
|
|
//bank_states = INITIAL_ACCESS;
|
|
o_m_valid = 1'b0;
|
|
|
|
// Before Access
|
|
// if (no_bank_misses) begin
|
|
// Dont do anything, next clock cycle it will switch back to (Fetch from mem)
|
|
// end else begin // Do logic to send requests to each bank (look through thread_track_bank regs)
|
|
//bank_has_access = banks_all_help & !(banks_to_wb) & !(banks_to_service);
|
|
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1) begin
|
|
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
|
//bank_has_access[bnk] = banks_all_help[bnk] && !thread_done[threads_in_banks[bnk]]; // Not sure
|
|
bank_has_access[bnk] = banks_all_help[bnk] && !thread_done[t_id]; // Not sure
|
|
if(thread_track_banks[bnk][t_id] == 1'b1 && bank_has_access[bnk] == 1'b1) begin
|
|
//bank_has_access[bnk] = 1'b1;
|
|
bank_access_data[bnk] = i_p_writedata[t_id];
|
|
bank_access_addr[bnk] = i_p_addr[t_id];
|
|
threads_in_banks[bnk] = t_id[1:0];
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
|
|
end
|
|
RE_ACCESS_PROCESSING:begin
|
|
// After Access
|
|
for (bnk = 0; bnk < NUMBER_BANKS; bnk = bnk + 1) begin
|
|
if(banks_ready[bnk]) begin // FIX to handle hits
|
|
thread_done[threads_in_banks[bnk]] = 1'b1;
|
|
o_p_readdata[threads_in_banks[bnk]] = data_from_bank[bnk];
|
|
if(i_p_read_or_write == 1'b0) begin
|
|
o_p_readdata_valid[threads_in_banks[bnk]] = 1'b1;
|
|
end
|
|
thread_track_banks[bnk][threads_in_banks[bnk]] = 1'b0; // Update that this thread does not need to be serviced again
|
|
// Added Oct 21
|
|
banks_to_service_temp[bnk] = 1'b0;
|
|
banks_to_wb_temp[bnk] = 1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
endcase
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
banks_to_service <= banks_to_service_temp;
|
|
banks_to_wb <= banks_to_wb_temp;
|
|
end
|
|
|
|
|
|
genvar bank_id;
|
|
generate
|
|
for (bank_id = 0; bank_id < NUMBER_BANKS; bank_id = bank_id + 1)
|
|
begin
|
|
//VX_alu vx_alu(
|
|
// .in_reg_data (in_reg_data[1:0]),
|
|
// .in_1 (in_a_reg_data[index_out_reg]),
|
|
// .in_2 (in_b_reg_data[index_out_reg]),
|
|
// .in_rs2_src (in_rs2_src),
|
|
// .in_itype_immed(in_itype_immed),
|
|
// .in_upper_immed(in_upper_immed),
|
|
// .in_alu_op (in_alu_op),
|
|
// .in_csr_data (in_csr_data),
|
|
// .in_curr_PC (in_curr_PC),
|
|
// .out_alu_result(VX_exe_mem_req.alu_result[index_out_reg])
|
|
//);
|
|
// bank VX_banks(
|
|
// .clk (clk),
|
|
// .rst (rst),
|
|
// //.state (bank_states[bank_id]),
|
|
// .state (state),
|
|
// .read_or_write (rd_or_wr),
|
|
// //.index (correct_index),
|
|
// //.tag (correct_tag),
|
|
// .addr (bank_access_addr[bank_id]),
|
|
// .writedata (bank_access_data[bank_id]),
|
|
// .fetched_write_data(i_m_readdata[(bank_id+1)*32-1 -: 32]),
|
|
// .valid (bank_has_access[bank_id]),
|
|
// .readdata (data_from_bank[bank_id]),
|
|
// .miss_cache (banks_missed[bank_id]),
|
|
// .w2m_needed (banks_wb_needed[bank_id]),
|
|
// .w2m_addr (banks_wb_addr[bank_id]),
|
|
// .e_data (o_m_writedata[(bank_id+1)*32-1 -: 32]),
|
|
// //.w2m_data (banks_wb_data[bank_id]),
|
|
// .ready (banks_ready[bank_id])
|
|
// //.valid_data (valid_in_set)
|
|
// //.read_miss (read_miss)
|
|
// );
|
|
|
|
VX_Cache_Bank bank_structure (
|
|
.clk (clk),
|
|
.state (state),
|
|
.read_or_write (rd_or_wr),
|
|
.valid_in (bank_has_access[bank_id]),
|
|
.actual_index (bank_access_addr[bank_id][14:7]), // fix when size changes
|
|
.o_tag (bank_access_addr[bank_id][31:15]), // fix when size changes
|
|
.block_offset (bank_access_addr[bank_id][6:5]),
|
|
.writedata (bank_access_data[bank_id]),
|
|
//.fetched_writedata (i_m_readdata[(bank_id+1)*32-1 -: 32]),
|
|
.fetched_writedata (i_m_readdata[bank_id[3:0]]),
|
|
.readdata (data_from_bank[bank_id]),
|
|
.hit (banks_ready[bank_id]),
|
|
//.miss (banks_missed[bank_id]),
|
|
.eviction_wb (banks_wb_needed[bank_id]),
|
|
.eviction_addr (banks_wb_addr[bank_id]),
|
|
//.data_evicted (o_m_writedata[(bank_id+1)*32-1 -: 32])
|
|
.data_evicted (o_m_writedata[bank_id[3:0]])
|
|
);
|
|
|
|
end
|
|
endgenerate
|
|
|
|
//end
|
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
|