21 lines
474 B
Systemverilog
21 lines
474 B
Systemverilog
`include "VX_platform.vh"
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module VX_bits_remove #(
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parameter N = 1,
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parameter S = 1,
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parameter POS = 0
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) (
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input wire [N-1:0] data_in,
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output wire [N-S-1:0] data_out
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);
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`UNUSED_VAR (data_in)
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if (POS == 0) begin
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assign data_out = data_in[N-1:S];
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end else if (POS == N) begin
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assign data_out = data_in[N-S-1:0];
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end else begin
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assign data_out = {data_in[N-1:(POS+S)], data_in[POS-1:0]};
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end
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endmodule |