felsabbagh3 3b49b82c46 GPR ASIC Working

2019-10-29 23:20:16 -04:00

..

vsim

Simulate debug

2019-10-29 14:28:20 -04:00

command.log

Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation

2019-10-28 14:49:55 -04:00

rf2_32x128_wm1_antenna.clf

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_ff_0p99v_0p99v_125c.avm

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_ff_0p99v_0p99v_125c.dat

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_ff_0p99v_0p99v_125c.db

Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation

2019-10-28 14:49:55 -04:00

rf2_32x128_wm1_ff_0p99v_0p99v_125c.lib

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_ff_0p99v_0p99v_125c.ps

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_rtl.v

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_ss_0p81v_0p81v_m40c.avm

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_ss_0p81v_0p81v_m40c.dat

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db

Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation

2019-10-28 14:49:55 -04:00

rf2_32x128_wm1_ss_0p81v_0p81v_m40c.lib

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_ss_0p81v_0p81v_m40c.ps

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_tt_0p90v_0p90v_25c.avm

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_tt_0p90v_0p90v_25c.dat

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_tt_0p90v_0p90v_25c.db

Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation

2019-10-28 14:49:55 -04:00

rf2_32x128_wm1_tt_0p90v_0p90v_25c.lib

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1_tt_0p90v_0p90v_25c.ps

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1.bitmap

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1.cpf

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1.ctl

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1.lef

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1.mdt

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1.memlib

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1.tv

Create the memory blocks with CLN28HPM

2019-10-17 15:38:48 -04:00

rf2_32x128_wm1.v

GPR ASIC Working

2019-10-29 23:20:16 -04:00