48 lines
1.8 KiB
Verilog
48 lines
1.8 KiB
Verilog
`include "VX_define.vh"
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module VX_dcache_arb (
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input wire req_select,
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// input request
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VX_cache_core_req_if in_core_req_if,
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// output 0 request
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VX_cache_core_req_if out0_core_req_if,
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// output 1 request
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VX_cache_core_req_if out1_core_req_if,
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// input 0 response
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VX_cache_core_rsp_if in0_core_rsp_if,
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// input 1 response
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VX_cache_core_rsp_if in1_core_rsp_if,
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// output response
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VX_cache_core_rsp_if out_core_rsp_if
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);
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assign out0_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{~req_select}};
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assign out0_core_req_if.rw = in_core_req_if.rw;
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assign out0_core_req_if.byteen = in_core_req_if.byteen;
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assign out0_core_req_if.addr = in_core_req_if.addr;
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assign out0_core_req_if.data = in_core_req_if.data;
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assign out0_core_req_if.tag = in_core_req_if.tag;
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assign out1_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{req_select}};
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assign out1_core_req_if.rw = in_core_req_if.rw;
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assign out1_core_req_if.byteen = in_core_req_if.byteen;
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assign out1_core_req_if.addr = in_core_req_if.addr;
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assign out1_core_req_if.data = in_core_req_if.data;
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assign out1_core_req_if.tag = in_core_req_if.tag;
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assign in_core_req_if.ready = req_select ? out1_core_req_if.ready : out0_core_req_if.ready;
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wire rsp_select0 = (| in0_core_rsp_if.valid);
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assign out_core_rsp_if.valid = rsp_select0 ? in0_core_rsp_if.valid : in1_core_rsp_if.valid;
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assign out_core_rsp_if.data = rsp_select0 ? in0_core_rsp_if.data : in1_core_rsp_if.data;
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assign out_core_rsp_if.tag = rsp_select0 ? in0_core_rsp_if.tag : in1_core_rsp_if.tag;
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assign in0_core_rsp_if.ready = out_core_rsp_if.ready && rsp_select0;
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assign in1_core_rsp_if.ready = out_core_rsp_if.ready && !rsp_select0;
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endmodule |