27 lines
740 B
Verilog
27 lines
740 B
Verilog
`ifndef VX_GPU_DCACHE_REQ
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`define VX_GPU_DCACHE_REQ
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`include "../generic_cache/VX_cache_config.vh"
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interface VX_gpu_dcache_req_inter #(
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parameter NUM_REQUESTS = 32
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) ();
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// Core Request
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wire [NUM_REQUESTS-1:0] core_req_valid;
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wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
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wire [NUM_REQUESTS-1:0][31:0] core_req_writedata;
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wire [NUM_REQUESTS-1:0][2:0] core_req_mem_read;
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wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write;
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wire [4:0] core_req_rd;
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wire [NUM_REQUESTS-1:0][1:0] core_req_wb;
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wire [`NW_BITS-1:0] core_req_warp_num;
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wire [31:0] core_req_pc;
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// Can't WB
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wire core_no_wb_slot;
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endinterface
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`endif |